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參數(shù)資料
| 型號： | Q67100-A6059 |
| 廠商： | SIEMENS AG |
| 英文描述： | Primary Rate Access Clock Generator and Transceiver PRACT |
| 中文描述： | 主速率接入時鐘發(fā)生器和收發(fā)PRACT |
| 文件頁數(shù)： | 14/53頁 |
| 文件大?。?/td> | 418K |
| 代理商： | Q67100-A6059 |
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HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Data Book
14
12.99
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to
terminate the burst operation prematurely. These methods include using another Read or Write
Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst
cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst
operation but leave the bank open for future Read or Write Commands to the same page of the
active bank. When interrupting a burst with another Read or Write Command care must be taken to
avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the
easiest method to use when terminating a burst operation before it has been completed. If a Burst
Stop command is issued during a burst write operation, then any residual data from the burst write
cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is
registered will be written to the memory.
A10
BA0
BA1
0
0
0
Bank 0
0
0
1
Bank 1
0
1
0
Bank 2
0
1
1
Bank 3
1
x
x
all Banks
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