參數(shù)資料
型號: Q67100-A6059
廠商: SIEMENS AG
英文描述: Primary Rate Access Clock Generator and Transceiver PRACT
中文描述: 主速率接入時鐘發(fā)生器和收發(fā)PRACT
文件頁數(shù): 26/53頁
文件大?。?/td> 418K
代理商: Q67100-A6059
HYB39S64400/800/160BT(L)
64MBit Synchronous DRAM
Semiconductor Group
25
5. Burst Write Operation
Extra data is ignored after
termination of a Burst.
DIN A3
T4
are registered on the same clock edge.
The first data element and the Write
NOP
(Burst Length = 4, CAS latency = 2, 3)
T0
Command
DQ’s
CLK
DIN A1
T2
NOP
DIN A0
Write A
T1
DIN A2
NOP
T3
SPT03790
T6
NOP
NOP
T5
NOP
NOP
T7
NOP
T8
don’t care
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