
PEB 22554
Functional Description E1
Semiconductor Group
66
09.98
– a correct FAS word in frame n + 2.
If the service word in frame n + 1 or the FAS word in frame n + 2 or both are not found
searching for the next FAS word will be start in frame n + 2 just after the previous frame
alignment signal.
Reaching the synchronous state causes a frame alignment recovery interrupt status
ISR2.FAR if enabled. Undisturbed operation starts with the beginning of the next
doubleframe.
A-Bit Access
If the QuadFALC detects a remote alarm indication in the received data stream the
interrupt status bit ISR2.RA will be set. With setting of bit XSW.XRA a remote alarm (RAI)
will be send to the far end.
By setting FMR2.AXRA the QuadFALC automatically transmit the remote alarm bit = 1 in
the outgoing data stream if the receiver detects a loss of frame alignment FRS0.LFA = 1.
If the receiver is in synchronous state FRS0.LFA = 0 the remote alarm bit will be reset.
Note: The A-bit may be processed via the system interface. Setting bit TSWM.TRA
enables transparency for the A bit in transmit direction (refer to
table 7
).
S
a
- Bit Access
As an extension for access to the S
a
-bits via registers RSA4-8/XSA4-8 an option is
implemented to allow the usage of internal S
a
-bit registers RSA4-8/XSA4-8 in
doubleframe format.
This function is enabled by setting FMR1.ENSA = 1 for the transmitter and
FMR1.RFS1/0 = 01 for the receiver. The QuadFALC works then internally with a
16-frame structure but no CRC multiframe alignment/generation is performed.
3.7.2
The multiframe structure shown in
table 7
is enabled by setting bit: FMR1.RFS1/0 for the
receiver and FMR1.XFS for the transmitter.
Multiframe
:
2 submultiframes = 2
×
8 frames
Frame alignment
:
refer to section Doubleframe Format
Multiframe alignment :
bit 1 of frames 1, 3, 5, 7, 9, 11 with the pattern ‘001011’
CRC bits
:
bit 1 of frames 0, 2, 4, 6, 8, 10, 12, 14
CRC block size
:
2048 bit (length of a submultiframe)
CRC procedure
:
CRC4, according to ITU-T Rec. G.704, G.706
CRC-Multiframe