參數(shù)資料
型號: PUMA68FV32006M-90
元件分類: PROM
英文描述: 1M X 32 FLASH 3.3V PROM MODULE, 90 ns, PQMA68
封裝: PLASTIC, LCC-68
文件頁數(shù): 7/21頁
文件大小: 174K
代理商: PUMA68FV32006M-90
PUMA 68FV32006/A - 90/12/15
Issue 1.3 : December 1999
15
The Autoselect command sequence allows the host system to access the manufacturer and devices codes,
and determine whether or not a sector is protected. See Command definitions table. This method is an
alternative to that shown in the autoselect codes table, which is intended for PROM programmers and requires
V
ID on address bit A9.
The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect mode, and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle containing a sector address (SA) and the address 02h in it, returns 01h if that sector is protected,
or 00h if it is unprotected. Refer to sector address table for valid sector address.
The system must write the reset command to exit the autoselect mode and return to reading array data.
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock
write cycles, followed by the program set-up command. The program address and data are writen next, which
in turn initiate the Embeded Program Algorithm. The system is not required to provide further controls or
timings. The device automaticlly provides internally generated program pulses and verify the programmed cell
margin. Command definitions table shows the address and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete, the device then returns to reading array data and ad-
dresses are no longer latched. The system can determine the status of the program operation by using DQ7 or
DQ6. See "Write Operation Status" for information on these status bits.
Any commands writen to the device during the Embedded Program Algorithm are ignored. Note that a hard-
ware reset immediatly terminates the programming opperation. The program command sequence should be
reinitiated once the device has reset to reading data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot from a "0" back to a "1".
Attempting to do so may halt the opperation and set DQ5 to "1", or cause the data Polling Algorithm to indicate
the opperation was sucessful. However, a succeeding read will show that the data is still "0". Only erase
operations can convert a "0" to a "1".
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.
Chip erase doesn't require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device automatically will program and verify the entire memory for an all
zero data pattern prior to electrical erase. The systems is not required to provide any controls or timings during
these operations.
Any commands written to the chip during the Embeded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately terminates the operation. The chip Erase Command se-
quence should be reinitiated once the device has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6 or DQ2. See "Write Operation
Status" for information on these status bits. When the Embeded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer latched.
Autoselect Command
Byte Programming
Chip Erase
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