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參數(shù)資料
| 型號： | PUMA68FV32006M-90 |
| 元件分類： | PROM |
| 英文描述： | 1M X 32 FLASH 3.3V PROM MODULE, 90 ns, PQMA68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 11/21頁 |
| 文件大?。?/td> | 174K |
| 代理商： | PUMA68FV32006M-90 |
PUMA 68FV32006/A - 90/12/15
Issue 1.3 : December 1999
19
Parameter
Limits
Unit
Comments
Min
Typ(1)
Max(2)
Sector Erase Time
Byte Programming Time
Chip Programming Time
Erase/Program Time
Chip Erase Time
1
15
9
300
9
27
100,000
1,000,000
16
sec
us
sec
cycles
Excludes 00H programming
prior to erasure
Excludes System level
Overhead
Excludes System level
Overhead
10,000 Min.
Notes : (1) 25OC, 3V V
CC, 100,000 cycles.
(2) Under work conditions 0f 90OC, V
CC 2.7V, 100,000 Cycles
The device is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transition. During power up the device automatically resets
the internal state machine in the Read mode. Also, with its controls register architecture , alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from Vcc power up
and power down transitions or system noise.
Noise pulses of less than 5ns (typical) on OE, CS, WE will not initiate a write cycle
Writing is inhibited by holding any one of OE=VIL, CS=VIH or WE=VIH. To initiate a write cycle CS and WE
must be logical zero while OE is a logical one.
Power-up of the device with WE=CS=VIL and OE=VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
Sectors of the device may be hardware protected at the users factory. The protection circuitry will disable both
program and erase functions for the protected sector(s). Requests to program or erase a protected sector will
be ignored by the device.
When Vcc is less than V
LKO, the device does not accept any write cycles. This protects data during Vcc power-
up and power-down. The command register and all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored untill Vcc is greater than V
LKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when Vcc is greater than V
LKO.
DATA PROTECTION
Low V
CC Write Inhibit
Write Pulse "Glitch" Protection
Logical Inhibit
Power Up Write Inhibit
Sector Protect
ERASE AND PROGRAMMING PERFORMANCE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PUMA68FV32006X-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| PUMA68FV32006X-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| PUMA68FV32006X-90 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| PUMA68FV32006XI-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| PUMA68FV32006XI-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
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