參數(shù)資料
型號(hào)： PUMA68FV32006M-90
元件分類(lèi)： PROM
英文描述： 1M X 32 FLASH 3.3V PROM MODULE, 90 ns, PQMA68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 10/21頁(yè)
文件大?。?/td> 174K
代理商： PUMA68FV32006M-90
PUMA 68FV32006/A - 90/12/15
Issue 1.3 : December 1999
18
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under
these conditions DQ5 produces a "1." This is a failure condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system tries to program a "1" to a location that is previously
programmed to "0." Only an erase operation can change a "0" back to a "1". Under this condition, the
device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a "1."
Under both these conditions, the system must issue the reset command to return the device to reading array
data.
D6 Toggle Bit
The device also features the "toggle bit" as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read data from the device will
result in D6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is
completed, D6 will stop toggling and valid data will be read on successive attempts. During programming, the
Toggle bit is valid after the rising edge of the forth WE pulse in the four write command pulse sequence. For
chip erase, the Toggle bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit is
active during the sector time-out.
After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3 will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, D3 may be
used to determine if the sector erase timer window is still open. If D3 is high the internally controlled erase
cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase opera-
tion is completed as indicated by Data Polling or Toggle Bit. If D3 is low , the device will accept additional
sector erase commands. To insure the command has been accepted, the software should check the status of
D3 prior to and following each subsequent sector erase command. If D3 were high on the second status
check, the command may not have been accepted.
D5
Exceeding Time Limits
D3 Sector Erase Timer
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PUMA68FV32006X-12 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:EEPROM
PUMA68FV32006X-15 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:EEPROM
PUMA68FV32006X-90 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:EEPROM
PUMA68FV32006XI-12 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:EEPROM
PUMA68FV32006XI-15 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:EEPROM
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