參數(shù)資料
型號: PTPS65910A1RSL
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: POWER SUPPLY SUPPORT CKT, PQCC48
封裝: 6 X 6 MM, 1 MM HEIGHT, GREEN, PLASTIC,VQFN-48
文件頁數(shù): 73/89頁
文件大?。?/td> 941K
代理商: PTPS65910A1RSL
PRODUCTPREVIEW
www.ti.com
SWCS046C – MARCH 2010 – REVISED JUNE 2010
7
6
5
4
3
2
1
0
VIO_KEEPON
VDD3_KEEPON
VDD2_KEEPON
VDD1_KEEPON
VRTC_KEEPON
I2CHS_KEEPON
THERM_KEEPON
CLKOUT32K_KEEPON
Bits
Field Name
Description
Type
Reset
7
THERM_KEEPON
When 1, thermal monitoring is maintained during device SLEEP state.
RW
0
When 0, thermal monitoring is turned off during device SLEEP state.
6
CLKOUT32K_KEEPO When 1, CLK32KOUT output is maintained during device SLEEP state.
RW
0
N
When 0, CLK32KOUT output is set low during device SLEEP state.
5
VRTC_KEEPON
When 1, LDO regulator full load capability (ACTIVE mode) is maintained
RW
0
during device SLEEP state.
When 0, the LDO regulator is set or stays in low power mode during
device SLEEP state.
4
I2CHS_KEEPON
When 1, high speed internal clock is maintained during device SLEEP
RW
0
state.
When 0, high speed internal clock is turned off during device SLEEP
state.
3
VDD3_KEEPON
When 1, VDD3 SMPS high power mode is maintained during device
RW
0
SLEEP state. No effect if VDD3 working mode is low power.
When 0, VDD3 SMPS low power mode is set during device SLEEP
state.
2
VDD2_KEEPON
If VDD2_EN1&2 control bit = 0 (default setting):
RW
0
When 1, VDD2 SMPS PWM mode is maintained during device SLEEP
state. No effect if VDD2 working mode is PFM.
When 0, VDD2 SMPS PFM mode is set during device SLEEP state.
1
VDD1_KEEPON
If VDD1_EN1&2 control bit=0 (default setting):
RW
0
When 1, VDD1 SMPS PWM mode is maintained during device SLEEP
state. No effect if VDD1 working mode is PFM.
When 0, VDD1 SMPS PFM mode is set during device SLEEP state.
0
VIO_KEEPON
If VIO_EN1&2 control bit=0 (default setting): When 1, VIO SMPS PWM
RW
0
mode is maintained during device SLEEP state. No effect if VIO working
mode is PFM.
When 0, VIO SMPS PFM mode is set during device SLEEP state.
Table 65. SLEEP_SET_LDO_OFF_REG
Address Offset
0x43
Physical Address
Instance
Description
Configuration Register turning-off LDO regulator during the SLEEP state of the device.
Corresponding *_KEEP_ON control bit in SLEEP_KEEP_RES_ON register should be 0 to make this
*_SET_OFF control bit effective
Type
RW
7
6
5
4
3
2
1
0
VPLL_SETOFF
VDIG2_SETOFF
VDIG1_SETOFF
VMMC_SETOFF
VDAC_SETOFF
VAUX2_SETOFF
VAUX1_SETOFF
VAUX33_SETOFF
Copyright 2010, Texas Instruments Incorporated
75
相關PDF資料
PDF描述
PTPS659106A1RSLR POWER SUPPLY SUPPORT CKT, PQCC48
PTPS659102A1RSLR POWER SUPPLY SUPPORT CKT, PQCC48
PTPS659104A1RSLR POWER SUPPLY SUPPORT CKT, PQCC48
PTPS659107A1RSL POWER SUPPLY SUPPORT CKT, PQCC48
PTPS659105A1RSLR POWER SUPPLY SUPPORT CKT, PQCC48
相關代理商/技術參數(shù)
參數(shù)描述
PTPS6591102A2ZRCR 制造商:TI 功能描述:TPS65911
PTPS6591102ZRC 制造商:TI 功能描述:TPS65911
PTPS6591104A2ZRCR 制造商:TI 功能描述:TPS65911
PTPS659110A2ZRC 制造商:TI 功能描述:TPS65911
PTPS659110A2ZRCR 制造商:TI 功能描述:TPS65911