參數(shù)資料
型號(hào)： PTPS65910A1RSL
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： POWER SUPPLY SUPPORT CKT, PQCC48
封裝： 6 X 6 MM, 1 MM HEIGHT, GREEN, PLASTIC,VQFN-48
文件頁(yè)數(shù)： 71/89頁(yè)
文件大?。?/td> 941K
代理商： PTPS65910A1RSL
PRODUCTPREVIEW
www.ti.com
SWCS046C – MARCH 2010 – REVISED JUNE 2010
Bits
Field Name
Description
Type
Reset
7
Reserved
Reserved bit
RO
0
R returns
0s
6
RTC_PWDN
When 1, disable the RTC digital domain (clock gating and reset of RTC
RW
1
registers and logic).
This register bit is not reset in BACKUP state. (EEPROM bit)
5
CK32K_CTRL
Internal 32-kHz clock source control bit (EEPROM bit):
RW
0
when 0, the internal 32-kHz clock source is the crystal oscillator or an
external 32-kHz clock in case the crystal oscillator is used in bypass
mode
when 1, the internal 32-kHz clock source is the RC oscillator.
4
SR_CTL_I2C_SEL
Smartreflex registers access control bit:
RW
0
when 0: access to smartreflex registers by smartreflex I2C
when 1: access to smartreflex registers by control I2C The smartreflex
registers are: VDD1_OP_REG, VDD1_SR_REG, VDD2_OP_REG and
VDD2_SR_REG.
3
DEV_OFF_RST
Write 1 will start an ACTIVE to OFF or SLEEP to OFF device state
RW
0
transition (switch-off event) and activate reset of the digital core.
2
DEV_ON
Write 1 will maintain the device on (ACTIVE or SLEEP device state) (if
RW
0
DEV_OFF = 0 and DEV_OFF_RST = 0).
1
DEV_SLP
Write 1 allows SLEEP device state (if DEV_OFF = 0 and
RW
0
DEV_OFF_RST = 0).
Write ‘0’ will start an SLEEP to ACTIVE device state transition (wake-up
event) (if DEV_OFF = 0 and DEV_OFF_RST = 0). This bit is cleared in
OFF state.
0
DEV_OFF
Write 1 will start an ACTIVE to OFF or SLEEP to OFF device state
RW
0
transition (switch-off event). This bit is cleared in OFF state.
Table 62. DEVCTRL2_REG
Address Offset
0x40
Physical Address
Instance
Description
Device control register
Type
RW
7
6
5
4
3
2
1
0
Reserved
TSLOT_LENGTH
IT_POL
PWON_LP_OFF
PWON_LP_RST
SLEEPSIG_POL
Bits
Field Name
Description
Type
Reset
7:6
Reserved
Reserved bit
RO
0x0
R returns
0s
5:4
TSLOT_LENGTH
Time slot duration programming (EEPROM bit):
RW
0x3
When 00 : 0 s
When 01 : 200 s
When 10 : 500 s
When 11 : 2 ms
3
SLEEPSIG_POL
When 1, SLEEP signal active high
RW
0
When 0, SLEEP signal active low
2
PWON_LP_OFF
When 1, allows device turn-off after a PWON Long Press (signal low).
RW
1
PWON_LP_RST
When 1, allows digital core reset when the device is OFF.
RW
0
IT_POL
INT1 interrupt pad polarity control signal (EEPROM bit):
RW
0
When 0, active low
When 1, active high
Copyright 2010, Texas Instruments Incorporated
73
相關(guān)PDF資料
PDF描述
PTPS659106A1RSLR POWER SUPPLY SUPPORT CKT, PQCC48
PTPS659102A1RSLR POWER SUPPLY SUPPORT CKT, PQCC48
PTPS659104A1RSLR POWER SUPPLY SUPPORT CKT, PQCC48
PTPS659107A1RSL POWER SUPPLY SUPPORT CKT, PQCC48
PTPS659105A1RSLR POWER SUPPLY SUPPORT CKT, PQCC48
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PTPS6591102A2ZRCR 制造商:TI 功能描述:TPS65911
PTPS6591102ZRC 制造商:TI 功能描述:TPS65911
PTPS6591104A2ZRCR 制造商:TI 功能描述:TPS65911
PTPS659110A2ZRC 制造商:TI 功能描述:TPS65911
PTPS659110A2ZRCR 制造商:TI 功能描述:TPS65911
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*