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PRODUCTPREVIEW
SWCS046C – MARCH 2010 – REVISED JUNE 2010
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Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
0x0
R returns
0s
3:2
SEL
Supply voltage (EEPROM bits):
RW
See (1)
SEL[1:0] = 00 : 1.0 V
SEL[1:0] = 01 : 1.1 V
SEL[1:0] = 10 : 1.2 V
SEL[1:0] = 11 : 1.8 V
1:0
ST
Supply state (EEPROM bits):
RW
0x0
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
(1)
The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 52. VAUX1_REG
Address Offset
0x32
Physical Address
Instance
Description
VAUX1 regulator control register
Type
RW
7
6
5
4
3
2
1
0
Reserved
SEL
ST
Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
0x0
R returns
0s
3:2
SEL
Supply voltage (EEPROM bits):
RW
See (1)
SEL[1:0] = 00 : 1.8 V
SEL[1:0] = 01 : 2.5 V
SEL[1:0] = 10 : 2.8 V
SEL[1:0] = 11 : 2.85 V
1:0
ST
Supply state (EEPROM bits):
RW
0x0
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
(1)
The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 53. VAUX2_REG
Address Offset
0x33
Physical Address
Instance
Description
VAUX2 regulator control register
Type
RW
7
6
5
4
3
2
1
0
Reserved
SEL
ST
68
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