參數(shù)資料
型號(hào)： PTPS659104A1RSLR
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： POWER SUPPLY SUPPORT CKT, PQCC48
封裝： 6 X 6 MM, 1 MM HEIGHT, GREEN, PLASTIC,VQFN-48
文件頁數(shù)： 70/89頁
文件大小： 941K
代理商： PTPS659104A1RSLR
PRODUCTPREVIEW
SWCS046C – MARCH 2010 – REVISED JUNE 2010
www.ti.com
7
6
5
4
3
2
1
0
Reserved
BBSEL
BBCHEN
Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
0x00
R returns
0s
2:1
BBSEL
Back up battery charge voltage selection:
RW
0x0
BBSEL[1:0] = 00 : 3.0 V
BBSEL[1:0] = 01 : 2.52 V
BBSEL[1:0] = 10 : 3.15 V
BBSEL[1:0] = 11 : VBAT
0
BBCHEN
Back up battery charge enable
RW
0
Table 60. DCDCCTRL_REG
Address Offset
0x3E
Physical Address
Instance
Description
DCDC control register
Type
RW
7
6
5
4
3
2
1
0
Reserved
VDD2_PSKIP
VDD1_PSKIP
VIO_PSKIP
DCDCCKEXT
DCDCCKSYNC
Bits
Field Name
Description
Type
Reset
7:6
Reserved
Reserved bit
RO
0x0
R returns
0s
5
VDD2_PSKIP
VDD2 pulse skip mode enable (EEPROM bit)
RW
1
4
VDD1_PSKIP
VDD1 pulse skip mode enable (EEPROM bit)
RW
1
3
VIO_PSKIP
VIO pulse skip mode enable (EEPROM bit)
RW
1
2
DCDCCKEXT
This signal control the muxing of the GPIO0 pad:
RW
0
When 0: this pad is a GPIO
When 1: this pad is used as input for an external clock used for the
synchronisation of the DCDCs
1:0
DCDCCKSYNC
DCDC clock configuration:
RW
0x3
DCDCCKSYNC[1:0] = 00 : no synchronization of DCDC clocks
DCDCCKSYNC[1:0] = 01 : DCDC synchronous clock with phase shift
DCDCCKSYNC[1:0] = 10 : no synchronization of DCDC clocks
DCDCCKSYNC[1:0] = 11 : DCDC synchronous clock
Table 61. DEVCTRL_REG
Address Offset
0x3F
Physical Address
Instance
Description
Device control register
Type
RW
7
6
5
4
3
2
1
0
Reserved
RTC_PWDN
CK32K_CTRL
DEV_ON
DEV_SLP
DEV_OFF
DEV_OFF_RST
SR_CTL_I2C_SEL
72
Copyright 2010, Texas Instruments Incorporated
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