參數(shù)資料
型號(hào)： PTPS659104A1RSLR
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： POWER SUPPLY SUPPORT CKT, PQCC48
封裝： 6 X 6 MM, 1 MM HEIGHT, GREEN, PLASTIC,VQFN-48
文件頁數(shù)： 25/89頁
文件大?。?/td> 941K
代理商： PTPS659104A1RSLR
PRODUCTPREVIEW
t
dSON1
1.8 V
t
dSON7
SWCS046-019
t
dSON8
Switch-off sequence
t
: Switch-on sequence
dSONT
1.8 V
1.2 V
3.3 V
1.8 V
1.2 V
t
dSON2
t
dSON3
t
dSON4
t
dSON5
t
dSON6
t
dSOFF2
t
dSOFF1
PWRHOLD
VIO/VFBIO
VPLL
VDD2/VFB2
VDD1/VFB1
VAUX2
VAUX33
CLK32KOUT
NRESPWRON
www.ti.com
SWCS046C – MARCH 2010 – REVISED JUNE 2010
Figure 3 shows the 01 Boot mode timing characteristics.
Figure 3. Boot Mode: BOOT1 = 0, BOOT0 = 1
Table 5 lists the 01 Boot mode timing characteristics.
Table 5. Boot Mode: BOOT1 = 0, BOOT0 = 1 Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tdSON1
PWRHOLD rising edge to VIO enable delay
66 × tCK32k = 2060
s
tdSON2
VIO to VPLL enable delay
64 × tCK32k = 2000
s
tdSON3
VPLL to VDD1 enable delay
64 × tCK32k = 2000
s
tdSON4
VDD1 to VDD2 enable delay
64 × tCK32k = 2000
s
tdSON5
VDD2 to VAUX2 enable delay
64 × tCK32k = 2000
s
VAUX2 to VAUX33 enable delay
64 × tCK32k = 2000
s
tdSON7
VAUX33 to CLK32KOUT enable delay
64 × tCK32k = 2000
s
tdSON8
CLK32KOUT to NRESPWON enable delay
64 × tCK32k = 2000
s
tdSONT
Total switch-on delay
16
ms
tdSOFF1
PWRHOLD falling edge to NRESPWON falling edge
2 × tCK32k = 62.5
s
tdSOFF1B
NRESPWON falling edge to CLK32KOUT low delay
3 × tCK32k = 92
s
tdSOFF2
PWRHOLD falling edge to supplies disable delay
5 × tCK32k = 154
s
Registers default setting: CK32K_CTRL = 0 (32-kHz quartz or external bypass clock is used), RTC_PWDN = 1
(RTC domain off), IT_POL = 0 (INt2 interrupt flag active low), VMBHI_IT_MSK = 0 (automatic switch-on on
battery plug), VMBCH_SEL = 11.
Copyright 2010, Texas Instruments Incorporated
31
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