參數(shù)資料
型號： PTPS659104A1RSLR
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： POWER SUPPLY SUPPORT CKT, PQCC48
封裝： 6 X 6 MM, 1 MM HEIGHT, GREEN, PLASTIC,VQFN-48
文件頁數(shù)： 36/89頁
文件大?。?/td> 941K
代理商： PTPS659104A1RSLR
PRODUCTPREVIEW
www.ti.com
SWCS046C – MARCH 2010 – REVISED JUNE 2010
Or interrupt flag active (default INT1 low) generates a power-on enable condition during a fixed delay (TDOINT1
pulse duration defined in section: power control timmings). interrupt sources expected (if enabled), when the
device is off:
–
RTC Alarm interrupt
–
First-time input voltage rising above VMBHI threshold (depending on the Boot mode used) and input
voltage > VMBCH threshold. The interrupt corresponding to this last condtion is the VMBCH_IT in
INT_STS_REG register.
Interrupt flag active generates a POWER ON enable condition during a fixed delay only when the device is in
OFF state (when NRESPWON signal is low). interrupt status register must be cleared first to allow device power
off during the tDOINT1 pulse duration.
GPIO_CKSYNC cannot be used to turn on the device, even if its associated interrupt is not masked.
Device power-on disable conditions:
PWRON signal low level during more than the long-press delay: PWON_LP_DELAY (can be disabled though
register programming). The interrupt corresponding to this condtion is PWRON_LP_IT in the INT_STS_REG
register.
Or Die temperature has reached the thermal shutdown threshold.
Or DEV_OFF or DEV_OFF_RST control bit set to 1 (value of DEV_OFF is cleared when the device is in OFF
state).
Device SLEEP enable conditions:
SLEEP signal low level (default, or high level depending on the programmed polarity)
And DEV_SLP control bit set to 1
And interrupt flag inactive (default INT1 high): no nonmasked interrupt pending
SLEEP state can be controlled by programming DEV_SLP and keeping the SLEEP signal floating, or it can be
controlled through the SLEEP signal setting DEV_SLP = 1 once after device turn-on .
SWITCH-ON/-OFF SEQUENCES
The power sequence is the automated switching on of the device resources when an off-to-active transition takes
place.
The device supports three embedded power sequences selectable by the device BOOT pins.
BOOT0
BOOT1
Processor Supported
0
AM3517, AM3505
1
0
OMAP3 Family, AM3715/03, DM3730/25
0
1
EEPROM sequence
Details of the boot sequence timing are given in SWITCH-ON/-OFF SEQUENCES AND TIMING. EEPROM
sequences can be used for specific power up sequence for corresponding application processor. For details of
EEPROM
sequence
refer
to
the
user
guides
on
the
product
folder:
CONTROL SIGNALS
SLEEP
When none of the device sleep-disable conditions are met, a falling edge (default, or rising edge, depending on
the programmed polarity) of this signal causes an ACTIVE-to-SLEEP state transition of the device. A rising edge
(default, or falling edge, depending on the programmed polarity) causes a transition back to ACTIVE state. This
input signal is level sensitive and no debouncing is applied.
While the device is in SLEEP state, predefined resources are automatically set in their low-power mode or off.
Copyright 2010, Texas Instruments Incorporated
41
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