參數(shù)資料
型號(hào)： PTPS659104A1RSLR
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： POWER SUPPLY SUPPORT CKT, PQCC48
封裝： 6 X 6 MM, 1 MM HEIGHT, GREEN, PLASTIC,VQFN-48
文件頁數(shù)： 54/89頁
文件大?。?/td> 941K
代理商： PTPS659104A1RSLR
PRODUCTPREVIEW
SWCS046C – MARCH 2010 – REVISED JUNE 2010
www.ti.com
7
6
5
4
3
2
1
0
Reserved
IT_ALARM
IT_TIMER
EVERY
IT_SLEEP_MASK_EN
Bits
Field Name
Description
Type
Reset
7:5
Reserved
Reserved bit
RO
0x0
R returns
0s
4
IT_SLEEP_MASK_E
1: Mask periodic interrupt while the TPS65910 device is in SLEEP mode.
RW
0
N
Interrupt event is back up in a register and occurred as soon as the
TPS65910 device is no more in SLEEP mode.
0: Normal mode, no interrupt masked
3
IT_ALARM
Enable one interrupt when the alarm value is reached (TC ALARM
RW
0
registers) by the TC registers
2
IT_TIMER
Enable periodic interrupt
RW
0
0: interrupt disabled
1: interrupt enabled
1:0
EVERY
Interrupt period
RW
0x0
00: every second
01: every minute
10: every hour
11: every day
Table 30. RTC_COMP_LSB_REG
Address Offset
0x13
Physical Address
Instance
Description
RTC compensation register (LSB)
Notes: This register must be written in 2-complement.
This means that to add one 32kHz oscillator period every hour, micro-controller needs to write FFFF into
RTC_COMP_MSB_REG & RTC_COMP_LSB_REG.
To remove one 32-kHz oscillator period every hour, micro-controller needs to write 0001 into
RTC_COMP_MSB_REG & RTC_COMP_LSB_REG.
The 7FFF value is forbidden.
Type
RW
7
6
5
4
3
2
1
0
RTC_COMP_LSB
Bits
Field Name
Description
Type
Reset
7:0
RTC_COMP_LSB
This register contains the number of 32-kHz periods to be added into the
RW
0x00
32-kHz counter every hour [LSB]
Table 31. RTC_COMP_MSB_REG
Address Offset
0x14
Physical Address
Instance
Description
RTC compensation register (MSB)
Notes: See RTC_COMP_LSB_REG Notes.
Type
RW
58
Copyright 2010, Texas Instruments Incorporated
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