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參數(shù)資料
| 型號： | PT7C4563UEX |
| 廠商： | Pericom |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REAL TIME CLOCK 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年，方波輸出 |
| 時(shí)間格式： | HH:MM:SS（24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 1.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | PT7C4563UEXDKR |
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PT0333(09/09)
Ver: 0
11
Data Sheet
PT7C4563
Real-time Clock Module (I2C Bus)
Data acknowledge response (ACK signal)
When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment
is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This
does not include instances where the master device intentionally does not generate an ACK signal.)
Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases
the SDA line and the receiver sets the SDA line to low (= acknowledge) level.
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the
falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the
transmitter.
When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave, that
indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a
STOP condition from the Master.
e)
Slave Address
The I
2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin,
slave addresses are allocated to each device.
All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device
responds to this communication only when the specified slave address it has received matches its own slave address.
Slave addresses have a fixed length of 7 bits. See table for the details.
An R/W bit is added to each 7-bit slave address during 8-bit transfers.
Slave address
R / W bit
Operation
Transfer data
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Read
A3 h
1 (= Read)
Write
A2 h
1
0
1
0
1
0 (= Write)
2. I2C Bus’s Basic Transfer Format
SCL from Master
1
2
89
SDA from transmitter
(sending side)
SDA from receiver
(receiving side)
Release SDA
Low active
ACK signal
S
Start indication
P
Stop indication
Sr
Restart indication
A
RTC Acknowledge
A
Master Acknowledge
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