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參數(shù)資料
| 型號： | PT7C4563UEX |
| 廠商： | Pericom |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REAL TIME CLOCK 8MSOP |
| 標準包裝： | 1 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，方波輸出 |
| 時間格式： | HH:MM:SS（24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 1.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 標準包裝 |
| 其它名稱： | PT7C4563UEXDKR |
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PT0333(09/09)
Ver: 0
4
Data Sheet
PT7C4563
Real-time Clock Module (I2C Bus)
Function Description
Overview of Functions
1.
Clock function
CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) year
that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2100.
2.
Alarm function
These devices have one alarm system that outputs interrupt signals from INTA for PT7C4563 or INT/OUT/SQW for PT7C4341
to CPU when the date, day of the week, hour, minute or second correspond to the setting. Each of them may output interrupt
signal separately at a specified time. The alarm may be selectable between on and off for matching alarm or repeating alarm.
3.
Programmable square wave output
A square wave output enable bit controls square wave output at pin 7. 4 frequencies are selectable: 1, 32, 1.024k, 32.768k Hz.
4.
Interface with CPU
Data is read and written via the I
2C bus interface using two signal lines: SCL (clock) and SDA (data).
Since the output of the I/O pin SDA is open drain, a pull-up resistor should be used on the circuit board if the CPU output I/O is
also open drain.
The SCL's maximum clock frequency is 400 kHz, which supports the I
2C bus's high-speed mode.
5.
Oscillator fail detect
When oscillator fail, OSF bit will be set.
6.
Oscillator enable/disable
Only time count chain can be enable or disable by STOP bit.
7.
Reset function
The PT7C4563 includes an internal reset circuit which is active whenever the oscillator is stopped. In the reset state the I
2C-bus
logic is initialized and all registers, including the address pointer, are cleared with the exception of bits FE, OSF, TD1, TD0,
TESTC and AE which are set to logic 1.
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