參數(shù)資料
型號: PT7C4563UEX
廠商: Pericom
文件頁數(shù): 19/20頁
文件大?。?/td> 0K
描述: IC REAL TIME CLOCK 8MSOP
標準包裝: 1
類型: 時鐘/日歷
特點: 警報器,閏年,方波輸出
時間格式: HH:MM:SS(24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 1.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 標準包裝
其它名稱: PT7C4563UEXDKR
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PT0333(09/09)
Ver: 0
8
Data Sheet
PT7C4563
Real-time Clock Module (I2C Bus)
6.
Alarm Register
PT7C4563: Alarm Register
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
Alarm: Minutes
AE
*1
M40
M20
M10
M8
M4
M2
M1
09
(default)
Undefined Undefined
Undefined
Undefined Undefined Undefined Undefined Undefined
Alarm: Hours
AE
*2
×
H20
H10
H8
H4
H2
H1
0A
(default)
Undefined
0
Undefined
Undefined Undefined Undefined Undefined Undefined
Alarm: Dates
AE
*3
×
D20
D10
D8
D4
D2
D1
0B
(default)
Undefined
0
Undefined
Undefined Undefined Undefined Undefined Undefined
Alarm: Weekday
AE
*4
×
W4
W2
W1
0C
(default)
Undefined
0
Undefined Undefined Undefined
*1 Note: Minute alarm enable bit.
*2 Note: Hour alarm enable bit.
*3 Note: Date alarm enable bit.
*4 Note: Weekday alarm enable bit.
Alarm Function
Related register
Register definition
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01
Control/status 2
×
AF
×
AIE
×
02
Seconds
OSF
S40
S20
S10
S8
S4
S2
S1
03
Minutes
×
M40
M20
M10
M8
M4
M2
M1
04
Hours
×
H20
H10
H8
H4
H2
H1
05
Dates
×
D20
D10
D8
D4
D2
D1
06
Days of the week
×
W4
W2
W1
09
Alarm: Minutes
AE
M40
M20
M10
M8
M4
M2
M1
0A
Alarm: Hours
AE
×
H20
H10
H8
H4
H2
H1
0B
Alarm: Dates
AE
×
D20
D10
D8
D4
D2
D1
0C
Alarm: Weekday
AE
×
W4
W2
W1
When one or more of these registers are loaded with a valid minute, hour, day or weekday and its corresponding bit Alarm Enable
(AE) is logic 0, then that information will be compared with the current minute, hour, day and weekday. When all enabled
comparisons first match, the Alarm Flag (AF) is set. AF will remain set until cleared by software. Once AF has been cleared it
will only be set again when the time increments to match the alarm condition once more. Alarm registers which have their bit AE
at logic 1 will be ignored.
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