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| 型號： | PSD601E1 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個可編程I/O,通用PLD有63個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，4K的位的SRAM，26我個可編程輸入/輸出，通用PLD的有63個輸入） |
| 文件頁數(shù)： | 21/84頁 |
| 文件大?。?/td> | 426K |
| 代理商： | PSD601E1 |
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PSD6XX Family
11-21
Loading and Reading the Micro
Cells
The GPLD Micro
Cells occupy a memory location in the MCU address space as defined
by the CSIOP (refer to the I/O section). The Flip-Flops in each of the 12 Micro
Cells can
be loaded from the data bus by a microcontroller write bus cycle to the Micro
Cell
(see I/O Port section for Micro
Cell Addresses). A “1” in the data bit that associates with
the Micro
Cell will load a “1” to the Flip-Flop, a “0” in the data bit will load a “0” to the
Flip-Flop. The loading bus cycle takes priority over other Flip-Flop inputs that include the
Preset, Clear and clock. See Table 11 for the data bits that are connected to the
Micro
Cells. The ability to load the flip-flops and read them back is useful in such
applications as loadable counters, shift registers, mailboxes or handshaking protocols.
PLDs
(cont.)
LD
1
1
0
Din
1
0
X
Clk
X
X
In
X
X
PR
X
X
CLR
X
X
Q
1
0
Normal Flip-Flop Function
Table 11. Micro
Cell Flip-Flop Loading
NOTE:
LD is “1” when the MCU writes to the Micro
Cell address
The Output Enable
The Micro
Cell can be connected to a PSD6XXE1 I/O pin as PLD output. The output
enable of each of the Port pin output driver is controlled by a single product term (.oe) from
the AND array ORed with the Direction Register output. Upon power up, if no output enable
(.oe) equation is defined and the pin is declared as a PLD output in PSDsoft, the pin is
enabled.
If the Micro
Cell output is declared as internal node and not as Port pin output in the
PSDabel file, then the Port pin can be used for other I/O functions. The internal node
feedback can be routed as an input to the AND array.
Input Micro
Cell
The Input Micro
Cells as shown in Figure 8 are used to latch, register or pass incoming
Port signals prior to driving them onto the PLD Input bus. The outputs of these Micro
Cells
can also be read by the microcontroller through the internal Data Bus. The GPLD has 23
Input Micro
Cells, one for each pin of Ports A, B and C (except PC2). The Input
Micro
Cells are individually configurable.
The enable/clock for the latch and flip-flop is driven by a multiplexor whose inputs are a
product term from the GPLD AND array and the MCU address strobe (ALE). Each
product term output is used to latch/clock four Input Micro
Cells. Port inputs [3:0] can be
controlled by one product term and [7:4] can be controlled by another one.
The Input Micro
Cell configurations are specified by equations written in PSDabel.
Outputs of the Micro
Cells can be read by the microcontroller via the “Input Micro
Cell”
buffer. See the I/O Port section on how to read the Micro
Cells.
Input Micro
Cells can use the ALE to latch the higher address bits (A31 – A16). The
latched addresses are routed to the PLD as inputs.
The Input Micro-Cell is particularly useful in handshaking communication applications
where two processors wish to pass data between each other through a commonly accessi-
ble storage. Figure 9 shows a typical configuration where the Master MCU writes to the Port
A Data Out Register that is read by the Slave MCU via the activation of the “Slave-Read”
output enable product term. The Slave MCU can write to Port A Input Micro
Cells by
activating the “Slave- Wr” product term. The Master MCU can then read the Input
Micro
Cells. The “Slave-Read” and “Slave-Wr” signals are product terms that are derived
from the Slave MCU inputs of RD, WR, and Slave_CS.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD601E1-15L | 制造商:WSI 功能描述: |
| PSD601E1-70J | 制造商:WSI 功能描述: 制造商:WSI 功能描述:16K X 16 OTPROM, 26 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| PSD601E1-70L | 制造商:WSI 功能描述: |
| PSD602E1-70L | 制造商:WSI 功能描述: |
| PSD603E1-70L | 制造商:WSI 功能描述: |
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