參數(shù)資料
型號: PSD601E1
英文描述: Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯,4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
中文描述: 現(xiàn)場可編程微控制器外圍設備和嵌入式微-細胞(可編程邏輯,4K的位的SRAM,26我個可編程輸入/輸出,通用PLD的有63個輸入)
文件頁數(shù): 12/84頁
文件大?。?/td> 426K
代理商: PSD601E1
PSD6XX Family
11-12
The PSD6XXE1
Functional
Blocks
The PSD6XXE1 consists of five major functional blocks:
J
PLD Block
J
Bus Interface
J
I/O Ports
J
Memory Block
J
Power Management Unit
The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable.
PLDs
The PLDs bring programmable logic functionality to the PSD6XXE1. After
specifying the logic for the PLDs by using the PSDabel tool in the PSDsoft suite, the logic
configuration is programmed into the device and available when power is applied.
The PLDs (DPLD, ECSPLD and GPLD) consist of an AND array. The GPLD architecture
includes 12 Output Micro
Cells in addition to the AND array. There are 23 Input
Micro
Cells that can be configured as inputs to the PLD. Figure 3 shows the organization
of the PLD.
The AND array is used to form product terms specified using the PSDabel tool in the
PSDsoft development system. When the inputs used in a term are true, the output is active.
The GPLD Input Bus consists of 63 signals as shown in Table 6. Both the true and
complement value of inputs are available to the AND array. The DPLD and ECSPLD Input
Busses consists of fewer inputs and is a subset of the 63 inputs.
Input Source
Input Name
Number of Signals
MCU Address Bus
A[15:0]*
16
MCU Control Signals
CNTL[2:0]
3
Reset
RST
1
Power Down
PDN
1
I/O Ports Inputs (Input Micro
Cells)
PA[7:0], PB[7:0]
PC[7:3], PC[1:0]
23
Port D Inputs
PD[2:0]
3
Page Register
PGR[3:0]
4
Port A or B Micro
Cell Feedback
Port C Micro
Cell Feedback
MCELLAB.FB[7:4]
4
MCELLC.FB[7:0]
8
Table 6. GPLD Inputs
*
NOTE:
The address inputs are A[19:4] in 80C51XA mode.
相關PDF資料
PDF描述
PSD602E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯,4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
PSD603E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯,4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
PSD612E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯,4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
PSD613E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯,4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
PSD703S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯,4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
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