參數(shù)資料
型號： PSD511B1
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設備（可編程邏輯，16K的位的SRAM，40余個可編程輸入/輸出，通用PLD的有61個輸入）
文件頁數(shù)： 77/130頁
文件大?。?/td> 704K
代理商： PSD511B1
PSD5XX Famly
6-77
Counter/Timer
Operation
(Cont.)
Counter/Timer Clock Input
All Counter/Timers 0 through 3 have a common clock source. The Counter/Timers are
clocked from the output of a highly flexible and high resolution Divisor unit. The Divisor’s
input is the external Clock input pin. The Divisor DIV is a number in the range of
4
<
= DIV
<
= 280. Refer to Table 22 for exact values of DIV for different clock values.
Figure 42 details the PSD5XX Counter clock generation.
The Counter/Timer CLOCK input
(External Clock input)
(DIV)
=
where DIV = N
*
K and N = (4 + DLCY).
The value of K depends on the Scale-Bit (Bit 0 in the Global Command Register) in the
“Global Command Register” , K = 8 when Scale-Bit is set to 1 and K = 1 when Scale-Bit is
set to 0. DLCY is the number of Delay Cycles in the range of 0
<
= DLCY
<
= 31 set up in the
Delay Cycle Register. The fastest clock to service the Counter/Timer is = (Clock input / 4).
The maximum External Clock input value is 28 MHz and the fastest internal count frequency
is 7.0 MHz, i.e., a resolution of 143 ns. (Higher resolution can be achieved by using in
conjunction with GPLD macrocells). The default value of DIV is 4 (following a reset both K
and DLCY contain zeroes).
Termnal Counts (TCs)
The terminal counts (TC0 – TC3) generated by the Counter/Timers are made available
at Port E as outputs or as feedbacks to the ZPLD. Refer to Table 27a for pin assignments.
The terminal counts can be used to concatenate the 16-bit Counter/Timers into a
larger counter. Only the trailing edge of the TC signal can be used as input to another
Counter/Timer. For example, concatenating CTU0 and CTU1 requires the following
PPLD equation in the PSDabel file:
mc2tmr1 = !tc0;
In order for a TC signal to come out, its respective bit in the Port E Special Function Out
Register must be set to 1. TC signals on Port E pins can be used as inputs to the ZPLD.
A TC signal goes high for the duration of at least four CLKIN periods whenever its
corresponding Timer Counting-Register overflows or underflows.
Figure 41 gives the timing relationship between CLKIN and the TC signal.
Figure 41. Timng Relationship Between CLKINand the TC Signal.
4 CLKIN PERIODS
CLKIN
TC - SIGNAL
30ns
30ns
NOTES:
1. Overflow occurs when a counter value changes from FFFFh to 0000h during incrementing.
2. Underflow occurs when a counter value changes from 0000h to FFFFh during decrementing.
相關PDF資料
PDF描述
PSD502B1 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
PSD503B1 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
PSD502B1-12U 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-204AE package; Similar to IRH7250 with optional Total Dose Rating of 1000kRads
PSD502B1-12UI 250V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-254AA package; A IRHM57264SE with Standard Packaging
PSD502B1-15J 600V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-257AA package. Also available in Radiation Levels up to 300KRad.; Similar to IRHY67C30CM with Optional Total Dose Rating of 300kRads
相關代理商/技術參數(shù)
參數(shù)描述
PSD511B1-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD511B1-12JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD511B1-12LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD511B1-12U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD511B1-12UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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