- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368228 > PSD511B1 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入) PDF資料下載
參數(shù)資料
| 型號： | PSD511B1 |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，40余個可編程輸入/輸出，通用PLD的有61個輸入） |
| 文件頁數(shù)： | 4/130頁 |
| 文件大?。?/td> | 704K |
| 代理商： | PSD511B1 |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁
PSD5XX Famly
6-4
General
Description
(Cont.)
At the core of the PSD5XX are dedicated ZPLDs based on the functions they perform:
J
Decoding ZPLD (DPLD)
J
General Purpose ZPLD (GPLD)
J
Peripheral ZPLD (PPLD)
All ZPLDs receive the same inputs through the ZPLD bus and are differentiated by their
output destinations. The Decoder PLD (DPLD ) has as its main function to perform address
space decoding for the internal I/O Ports, Peripherals, four blocks of EPROM, standby
SRAM and peripheral mode of Port A. The address decoding can be based on any address
input, control signal (RD, PSEN, etc.) and page logic. Address inputs originate from either
the microcontroller interface (ADIO Port) or other I/O Ports for additional decoding. The
DPLD also supports special requirements of 8031 architecture based designs that need to
store data in the EPROM or execute programs from the SRAM.
The general purpose PLD (GPLD) is a general purpose ZPLD that can be used to
implement state machines and logic . The GPLD has up to 61 inputs, 118 product terms,
24 flexible macrocells and 24 I/O pins that are connected to Ports A, B and E. The GPLD
can also decode the microcontroller address bus and generate chip selects to external
peripherals or memories.
The peripheral PLD (PPLD) generates outputs to the Counter/Timer unit and the Interrupt
Controller. The PPLD outputs to the Counter/Timer enable, disable or trigger counting or
time capture. This unique capability enables the user to implement in the PPLD the exact
conditions for the timer to count or generate an output. The PPLD also generates four
outputs to the Interrupt Controller which enables the user to define the exact conditions for
interrupt generation.
The ZPLDs are designed to consume minimum power using Zero Power design techniques.
A configuration bit (Turbo bit), that can be set by the MCU, will automatically place the
ZPLDs into standby if no inputs are changing. Any unused product terms will be turned off
during programming and will not consume any power in the system.
The PSD5XX has 40 I/O pins that are divided into 5 ports. Each I/O pin can be individually
configured to provide many functions. Ports A, B and E have the capability to be
configured as standard MCU I/O ports, GPLD I/O, latched address outputs for multiplexed
address/data controllers, or special function I/O (e. g., Counter/Timer and Interrupts).
Ports C and D are standard I/O ports that can also be configured as ZPLD inputs or data
bus for microcontrollers with non-multiplexed bus.
The PSD5XX can easily interface with no “glue-logic” to a variety of 8 and 16-bit
microcontrollers with a multiplexed or non-multiplexed bus. All of the control signals are
connected to the three ZPLDs enabling the user to generate timing and decoding signals for
external peripherals. For controllers that do not have a Reset output, the PSD5XX can
generate a RESET output based on its RESET input that includes hysteresis.
The Counter/Timer unit provides four 16 bit highly flexible Counter/Timers. Each
Counter/Timer has five modes of operation: pulse, waveform, event counting, time capture
and watchdog (Real Time Clock). Counter 2 can operate as a Watch Dog Timer. Each
Counter/Timer can be programmed to count up or down. The inputs to the Counter/Timer
unit, which enable/disable counting or triggering an operation, can originate from the PPLD
or directly from the pins. The maximum operating frequency of each counter is 7.5 MHz.
The input clock can be divided (up to 280) before driving the Counter/Timer unit using the 4
to 280 range prescaler .
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD502B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入) |
| PSD503B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入) |
| PSD502B1-12U | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-204AE package; Similar to IRH7250 with optional Total Dose Rating of 1000kRads |
| PSD502B1-12UI | 250V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-254AA package; A IRHM57264SE with Standard Packaging |
| PSD502B1-15J | 600V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-257AA package. Also available in Radiation Levels up to 300KRad.; Similar to IRHY67C30CM with Optional Total Dose Rating of 300kRads |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD511B1-12J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD511B1-12JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD511B1-12LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD511B1-12U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD511B1-12UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。