參數(shù)資料
型號(hào): PSD4235G2
英文描述: Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片)
中文描述: Flash在系統(tǒng)可編程外設(shè)的16位微控制器(用于16位微控制器的閃速在系統(tǒng)可編程外圍芯片)
文件頁(yè)數(shù): 59/114頁(yè)
文件大?。?/td> 567K
代理商: PSD4235G2
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Beta Information
PSD4000 Series
55
The
PSD4000
Functional
Blocks
(cont.)
Control
Register
Setting
Direction
Register
Setting
VM
Defined In
PSDsoft
Register
Setting
JTAG
Enable
Mode
Declare
pins only
0
1= output,
0= input
(Note 1)
MCU I/O
(Note 3)
NA
NA
Declare pins
and logic
equations
PLD I/O
NA
(Note 1)
NA
NA
Data Port
(Port F, G)
Selected for
MCU with
non-mux bus
NA
NA
NA
NA
Address Out
(Port E, F, G)
Declare
pins only
1
1 (Note 1)
NA
NA
Declare pins or
logic equation
Address In
(Port A,B,C,D,F) for input
NA
NA
NA
NA
Micro
Cells
Peripheral I/O
(Port F)
Logic equations
(PSEL0 & 1)
NA
NA
PIO bit =1
NA
JTAG ISP
(Note 2)
Declare pins
only
NA
NA
NA
JTAG_Enable
MCU Reset
Mode
Specify pin
logic level
NA
NA
NA
NA
Table 20. Port Operating Mode Settings
*
NA = Not Applicable
NOTE:
1. The direction of the Port A,B,C, and F pins are controlled by the Direction Register ORed with the
individual output enable product term (.oe) from the CPLD AND array.
2. Any of these three methods will enable JTAG pins on Port E.
3. Control Register setting is not applicable to Ports A, B and C.
9.4.2.1 MCU I/OMode
In the MCU I/O Mode, the microcontroller uses the PSD4000 ports to expand its own
I/O ports. By setting up the CSIOP space, the ports on the PSD4000 are mapped into the
microcontroller address space. The addresses of the ports are listed in Table 6.
A port pin can be put into MCU I/O mode by writing a
0
to the corresponding bit in the
Control Register (Port E, F and G). The MCU I/O direction may be changed by writing to
the corresponding bit in the Direction Register, or by the output enable product term. See
the subsection on the Direction Register in the
Port Registers
section. When the pin is
configured as an output, the content of the Data Out Register drives the pin. When config-
ured as an input, the microcontroller can read the port input through the Data In buffer.
See Figure 24.
Ports A, B and C do not have Control Registers, and are in MCU I/O mode by default.
They can be used for PLD I/O if they are specified in PSDsoft.
9.4.2.2 PLD I/OMode
The PLD I/O Mode uses a port as an input to the CPLD
s Input Micro
Cells, and/or as an
output from the CPLD
s Output Micro
Cells. The output can be tri-stated with a control
signal. This output enable control signal can be defined by a product term from the PLD, or
by setting the corresponding bit in the Direction Register to
0
. The corresponding bit in the
Direction Register must not be set to
1
if the pin is defined as a PLD input pin in PSDsoft.
The PLD I/O Mode is specified in PSDsoft by declaring the port pins, and then specifying
an equation in PSDsoft.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD4235G2-70U 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD4235G2-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2-90UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-12UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100