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參數(shù)資料
| 型號(hào)： | PSD4235G2-A-15U |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁(yè)數(shù)： | 2/104頁(yè) |
| 文件大小： | 1114K |
| 代理商： | PSD4235G2-A-15U |
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Obsolete
Product(s)
- Obsolete
Product(s)
Description
PSD4135G2, PSD4135G2V
Doc ID 7838 Rev 2
1.1
In-system programming (ISP) via JTAG
An IEEE 1149.1 compliant JTAG-ISP interface is included on the PSD enabling the entire
device (both Flash memories, the PLD, and all configuration) to be rapidly programmed
while soldered to the circuit board. This requires no MCU participation, which means the
PSD can be programmed anytime, even while completely blank.
The innovative JTAG interface to Flash memories is an industry first, solving key problems
faced by designers and manufacturing houses, such as:
1.1.1
First time programming
How do I get firmware into the Flash the very first time? JTAG is the answer, program the
PSD while blank with no MCU involvement.
1.1.2
Inventory build-up of pre-programmed devices
How do I maintain an accurate count of pre-programmed Flash memory and PLD devices
based on customer demand? How many and what version? JTAG is the answer, build your
hardware with blank PSDs soldered directly to the board and then custom program just
before they are shipped to customer. No more labels on chips and no more wasted
inventory.
1.1.3
Expensive sockets
How do I eliminate the need for expensive and unreliable sockets? JTAG is the answer.
Solder the PSD directly to the circuit board. Program first time and subsequent times with
JTAG. No need to handle devices and bend the fragile leads.
1.2
In-application programming (IAP)
Two independent Flash memory arrays are included so the MCU can execute code from one
memory while erasing and programming the other. Robust product firmware updates in the
field are possible over any communication channel (CAN, Ethernet, UART, J1850, etc) using
this unique architecture. Designers are relieved of these problems:
1.2.1
Simultaneous read and write to Flash memory
How can the MCU program the same memory from which it is executing code? It cannot.
The PSD allows the MCU to operate the two Flash memories concurrently, reading code
from one while erasing and programming the other during IAP.
1.2.2
Complex memory mapping
How can I map these two memories efficiently? A programmable decode PLD is embedded
in the PSD. The concurrent PSD memories can be mapped anywhere in MCU address
space, segment by segment with extremely high address resolution. As an option, the
secondary Flash memory can be swapped out of the system memory map when IAP is
complete. A built-in page register breaks the MCU address limit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD4235G2-A-20UI | 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80 |
| PSD813F2A-15JI | 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| PSD834F2VA-15MI | 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| PSD854F2A-90MT | 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| PSD854F2A-90UT | 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4235G2V-12UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2V-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4256G6V-10UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4-36 | 制造商:Tamura Corporation of America 功能描述: |
| PSD-45 | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:45W DC-DC Single Output Switching Power Supply |
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