參數(shù)資料
型號(hào)： PSD4235G2-A-15U
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁(yè)數(shù)： 12/104頁(yè)
文件大?。?/td> 1114K
代理商： PSD4235G2-A-15U
Obsolete
Product(s)
- Obsolete
Product(s)
PSD4135G2, PSD4135G2V
Pin description
Doc ID 7838 Rev 2
CNTL2
40
I
READ or other Control input pin, with multiple configurations. Depending on the MCU
interface selected, this pin can be:
1. PSEN - Program Select Enable, active low in code fetch bus cycle (80C51XA
mode).
2. BHE - high-byte enable, 16-bit data bus.
3. UDS - active low, Strobe for high data byte, 16-bit data bus mode.
4. SIZ0 - Byte enable input.
5. LSTRB - low Strobe input.
This pin is also connected to the PLDs.
RESET
39
I
Active low input. Resets I/O Ports, PLD macrocells and some of the Configuration
registers and JTAG registers. Must be low at Power-up. Reset also aborts any Flash
memory Program or Erase cycle that is currently in progress.
PA0-PA7
51-58
I/O
CMOS
or
Open
Drain
These pins make up Port A. These port pins are configurable and can have the
following functions:
1. MCU I/O - standard output or input port.
2. GPLD macrocell outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
PB0-PB7
61-68
I/O
CMOS
or
Open
Drain
These pins make up Port B. These port pins are configurable and can have the
following functions:
1. MCU I/O - standard output or input port.
2. GPLD macrocell outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
PC0-PC7
41-48
I/O
CMOS
or
Slew
Rate
These pins make up Port C. These port pins are configurable and can have the
following functions:
1. MCU I/O - standard output or input port.
2. External Chip Select (ECS0-ECS7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
PD0
79
I/O
CMOS
or
Open
Drain
PD0 pin of Port D. This port pin can be configured to have the following functions:
1. ALE/AS input - latches address on ADIO0-ADIO15.
2. AS input - latches address on ADIO0-ADIO15 on the rising edge.
3. MCU I/O - standard output or input port.
4. Transparent PLD input (can also be PLD input for address A16 and above).
PD1
80
I/O
CMOS
or
Open
Drain
PD1 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O - standard output or input port.
2. Transparent PLD input (can also be PLD input for address A16 and above).
3. CLKIN - clock input to the GPLD macrocells, the APD Unit’s Power-down counter,
and the GPLD AND Array.
Table 2.
Pin description (continued)
Pin name
Pin
Type
Description
相關(guān)PDF資料
PDF描述
PSD4235G2-A-20UI 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
PSD813F2A-15JI 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
PSD834F2VA-15MI 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
PSD854F2A-90MT 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
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