參數(shù)資料
型號(hào)： PSD4235G2-A-15U
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁(yè)數(shù)： 11/104頁(yè)
文件大小： 1114K
代理商： PSD4235G2-A-15U
Obsolete
Product(s)
- Obsolete
Product(s)
Pin description
PSD4135G2, PSD4135G2V
Doc ID 7838 Rev 2
2
Pin description
Table 2 describes the pin names and pin functions of the PSD4135G2 and PSD4135G2V.
Pins that have multiple names and/or functions are defined using PSDsoft Express.
Table 2.
Pin description
Pin name
Pin
Type
Description
ADIO0-
ADIO7
3-7
10-12
I/O
This is the lower Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If your MCU has a multiplexed address/data bus where the data is multiplexed with
the lower address bits, connect AD0-AD7 to this port.
2. If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this
port.
3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this
port.
ALE or AS latches the address. The PSD drives data out only if the READ signal is
active and one of the PSD functional blocks has been selected. The addresses on
this port are passed to the PLDs.
ADIO8-
ADIO15
13-20
I/O
This is the upper Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If your MCU has a multiplexed address/data bus where the data is multiplexed with
the upper address bits, connect A8-A15 to this port.
2. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this
port.
3. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to
this port.
ALE or AS latches the address. The PSD drives data out only if the READ signal is
active and one of the PSD functional blocks has been selected. The addresses on
this port are passed to the PLDs.
CNTL0
59
I
The following control signals can be connected to this pin, based on your MCU:
1. WR - active low, Write Strobe input.
2. R_W - active high, READ/active low WRITE input.
3. WRL - active low, WRITE to low-byte.
This pin is connected to the PLDs. Therefore, these signals can be used in decode
and other logic equations.
CNTL1
60
I
The following control signals can be connected to this pin, based on your MCU:
1. RD - active low, Read Strobe input.
2. E - E clock input.
3. DS - active low, Data Strobe input.
4. LDS - active low, Strobe for low data byte.
This pin is connected to the PLDs. Therefore, these signals can be used in decode
and other logic equations.
相關(guān)PDF資料
PDF描述
PSD4235G2-A-20UI 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
PSD813F2A-15JI 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
PSD834F2VA-15MI 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
PSD854F2A-90MT 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
PSD854F2A-90UT 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
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PSD4256G6V-10UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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