參數(shù)資料
型號(hào): PSD4235G2-A-15U
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝: PLASTIC, TQFP-80
文件頁(yè)數(shù): 18/104頁(yè)
文件大?。?/td> 1114K
代理商: PSD4235G2-A-15U
Obsolete
Product(s)
Product(s)
PSD architectural overview
PSD4135G2, PSD4135G2V
Doc ID 7838 Rev 2
3.3
I/O ports
The PSD4135G2 and PSD4135G2V have 52 I/O pins divided among seven ports (Port A, B,
C, D, E, F and G). Each I/O pin can be individually configured for different functions. Ports
can be configured as standard MCU I/O ports, PLD I/O, or latched address outputs for
microcontrollers using multiplexed address/data busses.
The JTAG pins can be enabled on Port E for in-system programming (ISP).
Ports F and G can also be configured as a data port for a non-multiplexed bus.
3.4
MCU bus interface
The PSD4135G2 and PSD4135G2V easily interface with most 16-bit microcontrollers that
have either multiplexed or non-multiplexed address/data busses. The devices are configured
to respond to the microcontroller’s control signals, which are also used as inputs to the
PLDs.
3.5
ISP via JTAG port
In-system programming can be performed through the JTAG pins on Port E. This serial
interface allows complete programming of the entire PSD4135G2/G2V devices. A blank
device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI,
TDO) can be multiplexed with other functions on Port E. Table 4 indicates the JTAG signals
pin assignments.
Table 3.
PLD I/O
Name
Inputs
Outputs
Product terms
Decode PLD (DPLD)
66
14
40
General purpose PLD (GPLD)
66
24
136
Table 4.
JTAG signals on port E
Port E pins
JTAG signal
PE0
TMS
PE1
TCK
PE2
TDI
PE3
TDO
PE4
TSTAT
PE5
TERR
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