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參數(shù)資料
| 型號： | PPC440GX-3CC533S |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Power PC 440GX Embedded Processor |
| 中文描述： | 32-BIT, 533 MHz, RISC PROCESSOR, CBGA552 |
| 封裝： | 25 X 25 MM, CERAMIC, FBGA-552 |
| 文件頁數(shù)： | 84/93頁 |
| 文件大?。?/td> | 794K |
| 代理商： | PPC440GX-3CC533S |
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440GX – Power PC 440GX Embedded Processor
84
AMCC
Revision 1.15 – August 30, 2007
Data Sheet
DDR SDRAM MemClkOut0 and Read Clock Delay
In operation, following the receipt of an address and read command from the PPC440GX, the SDRAM generates
data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GX using a DQS
signal that is delayed 1/4 of a cycle. In order to accommodate timing variations introduced by the system designs
using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to
be adjusted for minimum latency. This adjustment requires programming the Read Clock delay and the selection of
Stage 1, Stage 2, or Stage 3 data for sampling at RDSP.
DDR SDRAM Read Data Path
Read Clock
PLB Clk
MemClkOut0(0)
T
MD
T
RD
T
MD
min =
T
MD
max =
T
RD
min =
T
RD
max =
567ps
1705ps
183ps
-6ps
Stage 1
Stage 2
Stage 3
RDSP
PLB bus
FF,
XL
FF
FF
FF
Data
Read Select
(SDRAM0_TR1)
DQS
1/4
Cycle
Delay
PLB Clock
Programmed
Read Clock
Delay
D
C
Package pins
Mux
C
C
C
D
D
D
FF Timing:
T
IS
= Input setup time = 0.2ns
T
IH
= Input hold time = 0.1ns
T
P
= Propagation delay (D to Q or C to Q) =
ECC
FF: Flip-Flop
XL: Transparent Latch
Q
Q
Q
Q
0.4ns maximum
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| PPC440GX-3CC667C | 制造商:AppliedMicro 功能描述: |
| PPC440GX-3CC667S | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 440GX Embedded Processor |
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| PPC440GX-3CF533C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 440GX Embedded Processor |
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