參數(shù)資料
型號(hào): PPC440GRx-SpAfffTs
廠商: Applied Micro Circuits Corp.
英文描述: PowerPC 440GRx Embedded Processor
中文描述: 嵌入式處理器的PowerPC 440GRx
文件頁(yè)數(shù): 56/88頁(yè)
文件大?。?/td> 603K
代理商: PPC440GRX-SPAFFFTS
440GRx – PPC440GRx Embedded Processor
Preliminary Data Sheet
56
AMCC Proprietary
Revision 1.08 – October 15, 2007
Table 9. Signal Functional Description (Sheet 1 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to OV
DD
(EOV
DD
for Ethernet)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to OV
DD
(EOV
DD
for Ethernet)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
PCI Interface
PCIAD00:31
Address/Data bus (bidirectional).
I/O
3.3V PCI
PCIC0:3/BE0:3
PCI Command/Byte Enables
.
I/O
3.3V PCI
PCIClk
Provides timing to the PCI interface for PCI transactions.
I
3.3V PCI
1, 5
PCIDevSel
Indicates the driving device has decoded its address as the
target of the current access.
(PCI 2.2 specification requires 8.2k
Ω
pull up on host system).
I/O
3.3V PCI
PCIFrame
Driven by the current master to indicate beginning and
duration of an access.
(PCI 2.2 specification requires 8.2k
Ω
pull up on host system).
I/O
3.3V PCI
PCIGnt0/Req
Indicates that the specified agent is granted access to the
bus. When the internal arbiter is enabled, output is PCIGnt0.
When the internal arbiter is disabled, output is Req.
O
3.3V PCI
PCIGnt1:5
Indicates that the specified agent is granted access to the
bus. Used only when internal PCI arbiter enabled.
O
3.3V PCI
PCIIDSel
Used as a chip select during configuration read and write
transactions.
I
3.3V PCI
PCIINT
Level sensitive PCI interrupt.
O
3.3V PCI
PCIIRDY
Indicates initiating agent’s ability to complete the current data
phase of the transaction.
(PCI 2.2 specification requires 8.2k
Ω
pull up on host system).
I/O
3.3V PCI
PCIPar
Even parity.
I/O
3.3V PCI
PCIPErr
Reports data parity errors during all PCI transactions except a
Special Cycle.
(PCI 2.2 specification requires 8.2k
Ω
pull up on host system).
I/O
3.3V PCI
PCIReq0/Gnt
Indicates to the PCI arbiter that the specified agent wishes to
use the bus. When the internal arbiter is enabled, input is
PCIReq0. When internal arbiter is disabled, input is Gnt.
I
3.3V PCI
1, 4
PCIReq1:5
An indication to the PCI arbiter that the specified agent wishes
to use the bus. Used only when internal PCI arbiter enabled.
I
3.3V PCI
1, 4
PCIReset
Brings PCI device registers and logic to a consistent state.
O
3.3V PCI
PCISErr
Reports address parity errors, data parity errors on the
Special Cycle command, or other catastrophic system errors.
(PCI 2.2 specification requires 8.2k
Ω
pull up on host system).
I/O
3.3V PCI
PCIStop
Indicates the current target is requesting the master to stop
the current transaction.
(PCI 2.2 specification requires 8.2k
Ω
pull up on host system).
I/O
3.3V PCI
PCITRDY
I
ndicates the target agent’s ability to complete the current
data phase of the transaction.
(PCI 2.2 specification requires 8.2k
Ω
pull up on host system).
I/O
3.3V PCI
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