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參數(shù)資料
| 型號： | PPC440GRx-SpAfffTs |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440GRx Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 440GRx |
| 文件頁數(shù)： | 54/88頁 |
| 文件大?。?/td> | 603K |
| 代理商： | PPC440GRX-SPAFFFTS |
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440GRx – PPC440GRx Embedded Processor
Preliminary Data Sheet
54
AMCC Proprietary
Revision 1.08 – October 15, 2007
Signal Descriptions
The PPC440GRx embedded controller is packaged in a 456-ball enhanced plastic ball grid array (E-PBGA). The
following tables describe the package level pinout.
In the
Table 9
on page 56, each I/O signal is listed along with a short description of its function. Active-low signals
(for example, RAS) are marked with an overline. Please see
Table 5
on page 19 for the pin (ball) number to which
each signal is assigned.
Multiplexed Signals
Some signals are multiplexed on the same pin so that the pin can be used for different functions. In most cases,
the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same
pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in
Table 5
on page 19. It is expected that in any single application a particular pin will always be programmed to serve the
same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise
be possible.
Note:
Signals multiplexed with GPIO default to GPIO receivers and float after reset. Initialization software must configure
the GPIO registers for the desired function as described in the GPIO chapter of the user’s manual. Any of these signals
requiring a particular state prior to running initialization code must be terminated wit pull ups or pull downs
.
Multipurpose Signals
In addition to multiplexing, some pins are also multi-purpose. For example, the EBC peripheral controller address
pins (PerAddr) are used as outputs by the PPC440GRx to broadcast an address to external slave devices when
the PPC440GRx has control of the external bus. When during normal operation an external master gains
ownership of the external bus, these same pins are used as inputs which are driven by the external master and
received by the EBC in the PPC440GRx. In this example, the pins are also bidirectional, serving both as inputs and
outputs.
Table 7. Pin Summary
Group
No. of Pins
Signal pins, non-multiplexed
268
Signal pins, multiplexed
93
Total Signal Pins
361
AV
DD
1
AGND
1
EAV
DD
1
EAGND
1
OV
DD
30
SOV
DD
14
EOV
DD
12
V
DD
56
GND
197
Total Power Pins
313
Reserved
6
Total Pins
680
相關(guān)PDF資料 |
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| PPC440GX-3CC533S | Power PC 440GX Embedded Processor |
| PPC440GX-3CC667S | Power PC 440GX Embedded Processor |
| PPC440GX-3CF400C | Power PC 440GX Embedded Processor |
| PPC440GX-3CF533C | Power PC 440GX Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440GRX-STA400E | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440GRX-STA533E | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440GRX-STA533EZ | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440GRX-STA667E | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440GRX-SUA400E | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
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