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參數(shù)資料
| 型號： | PPC440GP-3RC500CZ |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Power PC 440GP Embedded Processor |
| 中文描述： | 32-BIT, 500 MHz, RISC PROCESSOR, CBGA552 |
| 封裝： | 25 X 25 MM, ROHS COMPLIANT, CERAMIC, BGA-552 |
| 文件頁數(shù)： | 74/83頁 |
| 文件大?。?/td> | 773K |
| 代理商： | PPC440GP-3RC500CZ |
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440GP – Power PC 440GP Embedded Processor
74
AMCC
Revision 1.07 – October 4, 2007
Data Sheet
DDR SDRAM Read Operation
The following examples of timing for DDR SDRAM read operations are based on the relationship between the
incoming data and the PLB clock signal. Since the PLB clock cannot be directly observed, the delay of
MemClkOut(0) relative to the PLB clock (T
MD
) is provided.
The internal Read Clock signal, like MemClkOut0, is derived from the PLB clock and can be delayed relative to the
PLB clock by programming the RDCT and RDCD fields in the SDRAM0_TR1 register. The delay can be
programmed from 0 to 1/2 cycle in steps using RDCT. Setting RDCD results in a 1/2 cycle delay plus the value set
in RDCT. The delay of Read Clock relative to the PLB clock (T
RD
) shown below assumes the programmable Read
Clock delay is set to zero.
I/O Timing—DDR SDRAM T
SD
and T
HD
Notes:
1. T
SD
and T
HD
are measured under worst case conditions.
2. The time values in the table include 1/4 of a cycle at the indicated clock speed.
3. To obtain adjusted T
SD
and T
HD
values for lower clock frequencies, subtract 1.875 ns from the values in the table and add
1/4 of the cycle time for the lower clock frequency (e.g., T
SD
- 1.875 + 0.25T
CYC
).
Clock Speed (MHz)
Signal Names
Reference Signal
T
SD
(ns)
T
HD
(ns)
133
MemData00:07, DM0
DQS0
1.375
1.375
133
MemData08:15, DM1
DQS1
1.375
1.375
133
MemData16:23, DM2
DQS2
1.375
1.375
133
MemData24:31, DM3
DQS3
1.375
1.375
133
MemData32:39, DM4
DQS4
1.375
1.375
133
MemData40:47, DM5
DQS5
1.375
1.375
133
MemData48:55, DM6
DQS6
1.375
1.375
133
MemData56:63, DM7
DQS7
1.375
1.375
133
ECC0:7, DM8
DQS8
1.375
1.375
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