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參數(shù)資料
| 型號： | PPC440GP-3RC500CZ |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Power PC 440GP Embedded Processor |
| 中文描述： | 32-BIT, 500 MHz, RISC PROCESSOR, CBGA552 |
| 封裝： | 25 X 25 MM, ROHS COMPLIANT, CERAMIC, BGA-552 |
| 文件頁數(shù)： | 12/83頁 |
| 文件大小： | 773K |
| 代理商： | PPC440GP-3RC500CZ |
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440GP – Power PC 440GP Embedded Processor
12
AMCC
Revision 1.07 – October 4, 2007
Data Sheet
Ability to boot from PCI-X bus memory
Error tracking/status
Supports initiation of transfer to the following address spaces:
- Single beat I/O reads and writes
- Single beat and burst memory reads and writes
- Single beat configuration reads and writes (type 0 and type 1)
- Single beat special cycles
DDR SDRAM Memory Controller
The Double Data Rate (DDR) SDRAM memory controller supports industry standard 184-pin DIMMs and other
discrete devices. Up to four 512MB logical banks are supported in limited configurations. Global memory timings,
address and bank sizes, and memory addressing modes are programmable.
Features include:
Registered and non-registered industry standard DIMMs and other discrete devices
32- or 64-bit memory interface with optional 8-bit ECC (SEC/DED)
Sustainable 2.1GB/s peak bandwidth at 133MHz
SSTL_2 logic
1 to 4 chip selects
CAS latencies of 2, 2.5 and 3 supported
PC200/266 support
Page mode accesses (up to eight open pages) with configurable paging policy
Programmable address mapping and timing
Hardware and software initiated self-refresh
Power management (self-refresh, suspend, sleep)
External Peripheral Bus Controller (EBC)
Features include:
Up to eight ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported
Up to 66.66MHz operation (266MB/s)
Burst and non-burst devices
8-, 16-, 32-bit byte-addressable data bus
32-bit address, 4GB address space
Peripheral Device pacing with external “Ready”
Latch data on Ready, synchronous or asynchronous
Programmable access timing per device
- 256 Wait States for non-burst
- 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
- Programmable CSon, CSoff relative to address
- Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
Programmable address mapping
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