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Part Number 440GP
Revision 1.07 – October 4, 2007
AMCC
1
440GP
Power PC 440GP Embedded Processor
Data Sheet
Features
PowerPC
440 processor core operating up to
500MHz with 32KB I- and D-caches
On-chip 8KB SRAM
Selectable processor:bus clock ratios of 3:1, 4:1,
5:1, 5:2, 7:2
Double Data Rate (DDR) Synchronous DRAM
(SDRAM) 32/64-bit interface operating up to
133MHz
External Peripheral Bus for up to eight devices
with external mastering
DMA support for external peripherals, internal
UART and memory
PCI-X V1.0a interface (32 or 64 bits, up to
133MHz) with support for conventional PCI V2.2
Two Ethernet 10/100Mbps half- or full-duplex
interfaces. Operational modes supported are MII
and RMII.
Programmable Interrupt Controller supports
interrupts from a variety of sources.
Programmable General Purpose Timers (GPT)
Two serial ports (16750 compatible UART)
Two IIC interfaces
General Purpose I/O (GPIO) interface available
JTAG interface for board level testing
Internal Processor Local Bus (PLB) runs at DDR
SDRAM interface frequency
Processor can boot from PCI memory
Available in ceramic (RoHs and non-RoHS
compliant versions) and plastic packages.
Description
Designed specifically to address high-end embedded
applications, the PowerPC 440GP (PPC440GP)
provides a high-performance, low power solution that
interfaces to a wide range of peripherals by
incorporating on-chip power management features
and lower power dissipation.
This chip contains a high-performance RISC
processor core, DDR SDRAM controller,8KB SRAM,
PCI-X bus interface, Ethernet interfaces, control for
external ROM and peripherals, DMA with scatter-
gather support, serial ports, IIC interface, and general
purpose I/O.
Technology: CMOS SA-27E, 0.18
μ
m (0.11 L
eff
)
Packages: 25mm, 552-ball Ceramic Ball Grid Array
(CBGA) or Plastic Ball Grid Array (PBGA) in standard
or RoHS compliant versions
Power (estimated): Less than:
4.0W in normal mode
1.0W in sleep mode
Supply voltages required: 3.3V, 2.5V, 1.8V