參數(shù)資料
型號： PPC440GP-3RC466CZ
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： Power PC 440GP Embedded Processor
中文描述： 32-BIT, 466 MHz, RISC PROCESSOR, CBGA552
封裝： 25 X 25 MM, ROHS COMPLIANT, CERAMIC, BGA-552
文件頁數(shù)： 51/83頁
文件大?。?/td> 773K
代理商： PPC440GP-3RC466CZ
440GP – Power PC 440GP Embedded Processor
AMCC
51
Revision 1.07 – October 4, 2007
Data Sheet
External Master Peripheral Interface
BusReq
Bus Request. Used when the PPC440GP needs to regain control
of peripheral interface from an external master.
O
5V tolerant
3.3V LVTTL
ExtAck
External Acknowledgement. Used by the PPC440GP to indicate
that a data transfer occurred.
O
5V tolerant
3.3V LVTTL
ExtReq
External Request. Used by an external master to indicate it is
prepared to transfer data.
I
5V tolerant
3.3V LVTTL
1, 4
ExtReset
Peripheral Reset. Used by an external master and by
synchronous peripheral slaves.
O
5V tolerant
3.3V LVTTL
HoldAck
Hold Acknowledge. Used by the PPC440GP to transfer ownership
of peripheral bus to an external master.
O
5V tolerant
3.3V LVTTL
HoldReq
Hold Request. Used by an external master to request ownership
of the peripheral bus.
I
5V tolerant
3.3V LVTTL
1, 5
PerClk
Peripheral Clock. Used by an external master and by synchronous
peripheral slaves.
O
5V tolerant
3.3V LVTTL
PerErr
External Error. Used as an input to record external master errors
and external slave peripheral errors.
I/O
5V tolerant
3.3V LVTTL
1, 5
UART Peripheral Interface
UARTSerClk
Serial clock input that provides an alternative to the internally
generated serial clock. Used in cases where the allowable
internally generated clock rates are not satisfactory. This input can
be individually connected to either or both UART0 and UART1.
I
5V tolerant
3.3V LVTTL
1, 4
UART0_Rx
UART0 Receive data.
I
5V tolerant
3.3V LVTTL
1, 4
UART0_Tx
UART0 Transmit data.
O
5V tolerant
3.3V LVTTL
4
UART0_DCD
UART0 Data Carrier Detect.
I
5V tolerant
3.3V LVTTL
6
UART0_DSR
UART0 Data Set Ready.
I
5V tolerant
3.3V LVTTL
6
UART0_CTS
UART0 Clear To Send.
I
5V tolerant
3.3V LVTTL
1, 4
UART0_DTR
UART0 Data Terminal Ready.
O
5V tolerant
3.3V LVTTL
4
UART0_RTS
UART0 Request To Send.
O
5V tolerant
3.3V LVTTL
4
UART0_RI
UART0 Ring Indicator.
I
5V tolerant
3.3V LVTTL
1, 4
UART1_Rx
UART1 Receive data.
I/O
5V tolerant
3.3V LVTTL
1, 4
UART1_Tx
UART1 Transmit data.
I/O
5V tolerant
3.3V LVTTL
1, 4
UART1_DSR/CTS
UART1 Data Set Ready or Clear To Send. The choice is
determined by a DCR register bit setting.
I/O
5V tolerant
3.3V LVTTL
1, 4
Signal Functional Description
(Sheet 4 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V, 10k
Ω
to 5V
)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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