參數(shù)資料
型號(hào)： PPC405GPR-3KB400
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： Power PC 405GPr Embedded Processor
中文描述： 32-BIT, 400 MHz, RISC PROCESSOR, PBGA456
封裝： 27 X 27 MM, LEAD FREE, PLASTIC, EBGA-456
文件頁(yè)數(shù)： 29/57頁(yè)
文件大?。?/td> 614K
代理商： PPC405GPR-3KB400
405GPr – Power PC 405GPr Embedded Processor
AMCC
29
Revision 2.04 – September 7, 2007
Data Sheet
Pull-Up and Pull-Down Resistors
Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an
appropriate state. The recommended pull-up value of 3k
Ω
to +3.3V (10k
Ω
to +5V can be used on 5V tolerant I/Os)
and pull-down value of 1k
Ω
to GND, applies only to individually terminated signals. To prevent possible damage to
the device, I/Os capable of becoming outputs
must never
be tied together and terminated through a common
resistor.
If your system-level test methodology permits, input-only signals can be connected together and terminated
through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that
the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into the
PPC405GPr.
Unused I/Os
For some interfaces, it is possible to turn off input receivers for some or all of the signals by means of bit settings in
register CPC0_CR1. When this gating capability is applied to unused signals, it is not necessary to terminate them.
Refer to the
PowerPC 405GPr Embedded Processor User’s Manual
for details.
If receiver gating is not used, termination of some pins may be necessary when they are unused. Although the
PPC405GPr requires only the pull-up and pull-down terminations as specified in the “Signal Functional
Description” on page 30, good design practice is to terminate all unused inputs or to configure I/Os such that they
always drive. If unused, and receiver gating is not used, the peripheral, SDRAM, and PCI buses should be
configured and terminated as follows:
Peripheral interface—PerAddr0:31, PerData0:31, and all of the control signals are driven by default. Terminate
PerReady high and PerError low.
SDRAM—Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the PPC405GPr to
actively drive all of the SDRAM address, data, and control signals.
PCI—The PCI pull-up requirements given in the Signal Functional Description apply only when the PCI
interface is being used. When the PCI bridge is unused, configure the PCI controller to park on the bus and
actively drive PCIAD31:0, PCIC3:0[BE3:0], and the remaining PCI control signals by doing the following:
- Strap the PPC405GPr to disable the internal PCI arbiter and to operate the PCI interface in synchronous
mode.
- Individually connect PCISErr, PCIPErr, PCITRDY, and PCIStop through 3k
Ω
resistors to +3.3V.
- Terminate PCIReq1:5 to +3.3V.
- Terminate PCIReq0[Gnt] to GND.
External Bus Control Signals
All peripheral bus control signals (PerCS0:7, PerR/W, PerWBE0:3, PerOE, PerWE, PerBLast, HoldAck, ExtAck)
are set to the high-impedance state when ExtReset=0. In addition, as detailed in the
PowerPC 405GPr Embedded
Processor User’s Manual
, the peripheral bus controller can be programmed via EBC0_CFG to float some of these
control signals between transactions and/or when an external master owns the peripheral bus. As a result, a pull-
up resistor should be added to those control signals where an undriven state may affect any devices receiving that
particular signal.
The following table lists all of the I/O signals provided by the PPC405GPr. Please refer to “Signals Listed
Alphabetically” on page 16 for the pin number to which each signal is assigned.
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