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| 型號： | PowerPC 603 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 5/54頁 |
| 文件大小： | 325K |
| 代理商： | POWERPC 603 |
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RISC Microprocessor Division
Page 5
There are many characteristics found in common among contemporary superscalar processors. One
characteristic is the ability to execute multiple instructions in parallel. To enable this, superscalar
processors contain multiple functional units, and they allow the fetching, issuing (dispatching), and
retiring of multiple instructions in one clock cycle.
Superscalar processors typically contain a register set with multiple read/write ports to allow multiple
instructions in execution to access data simultaneously. Most superscalar processors also have
separate floating-point and integer register sets.
The key focus of superscalar processors is to increase overall instruction throughput by keeping the
instruction pipeline free of stalls. Mechanisms exist to avoid false dependencies between instructions;
instructions should be allowed to dispatch and execute until they are forced to stall due to change in
instruction flow, lack of resources, or true data dependencies.
To allow the free flow of execution, most superscalar processors allow out-of-order execution of
instructions. However, a mechanism must exist for bringing the instructions back in program order
when they complete executing.
The primary reasons the instruction flow can stall within a superscalar processor are changes in
instruction flow, resource constraints, and data dependencies. By understanding the flow mechanism,
and being aware of the situations that can cause stalls, one can write code that avoids these situations
and thereby executes faster.
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