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參數(shù)資料
| 型號： | PowerPC 603 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 29/54頁 |
| 文件大?。?/td> | 325K |
| 代理商： | POWERPC 603 |
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RISC Microprocessor Division
Page 29
The Floating-Point Unit consists of four stages: Multiplier, Adder, Normalizer, and Exception, which are
organized conceptually as shown. The Multiplier stage is a single precision multiplier that every FP
instruction must pass through. No instruction can enter the FP unit if the Multiplier is occupied. Double
precision operations will cause the Multiplier to be occupied for two consecutive clocks. The Adder
always takes a single clock. Typically, instructions will flow through these stages without stalling unless
a stall in the Normalize or Exception stage blocks the instruction pipeline flow. The FP register file only
supports a single write-back port from the rename registers.
The Normalizer stage can cause delays of up to several clocks. The number of clocks that
normalization takes is data-dependent. When the normalizer stalls, it prevents instructions in the
Multiplier or Adder stages from stepping through.
To prevent potential speed path problems, an additional stage exists after the normalization stage. This
stage is simply a holding stage and floating-point instructions use up one clock cycle to pass through it.
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