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參數(shù)資料
| 型號(hào)： | PowerPC 603 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 11/54頁 |
| 文件大?。?/td> | 325K |
| 代理商： | POWERPC 603 |
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RISC Microprocessor Division
Page 11
The
fetcher
fetches up to two instructions per clock into the IQ, where they appear in the lowest
available slots. The
dispatcher
then dispatches up to two instructions from the IQ to the execution
units (excluding the BPU, which scans instructions as they are brought in by the fetcher). The
dispatcher also performs source and destination dependency checking and determines dispatch
serializations. Each instruction dispatched has an entry created for it in the completion queue.
When an execution unit has finished processing an instruction, it signals the completion unit, and the
instruction’s entry in the completion queue is marked “finished.” Up to two finished instructions per
clock may be retired (removed) from the completion queue. When an instruction is retired, the
architectural registers are updated.
Note that fetching, dispatching, and retiring of instructions is done in program order, but executing and
finishing can be done out-of-order and in parallel.
In a pipelined architecture, anything that prevents an instruction from moving from one stage of a
pipeline to the next is known as a stall. Resource checks must be performed to see if stalls will occur.
The rest of this paper discusses how and where stalls can occur in the instruction pipeline.
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