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參數(shù)資料
| 型號(hào)： | PM7383 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | FRAME ENGINE AND DATA LINK MANAGER 32A256 |
| 中文描述： | 框架引擎和數(shù)據(jù)鏈路管理32A256 |
| 文件頁(yè)數(shù)： | 57/231頁(yè) |
| 文件大?。?/td> | 1947K |
| 代理商： | PM7383 |
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RELEASED
DATASHEET
PM7383 FREEDM-32A256
ISSUE 1
PMC-2010336
FRAME ENGINE AND DATA LINK MANAGER 32A256
PROPRIETARY AND CONFIDENTIAL
49
are serviced. This cycle is used by the channel assigner downstream for host
microprocessor accesses to the provisioning RAMs.
8.3.4 Channel Assigner
The channel assigner block determines the channel number of the data byte
currently being processed. The block contains a 1024 word channel provision
RAM. The address of the RAM is constructed from concatenating the link
number and the time-slot number of the current data byte. The fields of each
RAM word include the channel number and a time-slot enable flag. The time-slot
enable flag labels the current time-slot as belonging to the channel indicted by
the channel number field.
8.3.5 Loopback Controller
The loopback controller block implements the channel based diagnostic loopback
function. Every valid data byte belonging to a channel with diagnostic loopback
enabled from the Transmit HDLC Processor / Partial Packet Buffer block
(THDL256) is written into a 64 word FIFO. The loopback controller monitors for
an idle time-slot or a time-slot carrying a channel with diagnostic loopback
enabled. If either conditions hold, the current data byte is replaced by data
retrieved from the loopback data FIFO.
8.4 Receive HDLC Processor / Partial Packet Buffer
The Receive HDLC Processor / Partial Packet Buffer block (RHDL256)
processes up to 256 synchronous transmission HDLC data streams. Each
channel can be individually configured to perform flag sequence detection, bit de-
stuffing and CRC-CCITT or CRC-32 verification. The packet data is written into
the partial packet buffer. At the end of a frame, packet status including CRC
error, octet alignment error and maximum length violation are also loaded into the
partial packet buffer. Alternatively, a channel can be provisioned as transparent,
in which case, the HDLC data stream is passed to the partial packet buffer
processor verbatim.
There is a natural precedence in the alarms detectable on a receive packet.
Once a packet exceeds the programmable maximum packet length, no further
processing is performed on it. Thus, octet alignment detection, FCS verification
and abort recognition are squelched on packets with a maximum length violation.
An abort indication squelches octet alignment detection, minimum packet length
violations, and FCS verification. In addition, FCS verification is only performed
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PM7383-PI | FRAME ENGINE AND DATA LINK MANAGER 32A256 |
| PM7384 | Frame Engine and Data Link Manager |
| PM7384-BI | FRAME ENGINE AND DATA LINK MANAGER 84P672 |
| PM7385 | Frame Engine and Data Link Manager |
| PM7385-BI | 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER WITH ANY-PHY PACKET INTERFACE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PM7383-PI | 制造商:PMC 制造商全稱:PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER 32A256 |
| PM7384 | 制造商:PMC 制造商全稱:PMC 功能描述:Frame Engine and Data Link Manager |
| PM7384-BI | 制造商:PMC 制造商全稱:PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER 84P672 |
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