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RELEASED
DATA SHEET
PM7382 FREEDM-32P256
ISSUE 3
PMC-2010333
FRAME ENGINE AND DATA LINK MANAGER 32P256
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
238
Register 0x48C – 0x4FC : TCAS Links #3 to #31 Configuration
Bit
Type
Function
Default
Bit 31
to
Bit 3
Unused
XXXXXXXXH
Bit 2
R/W
MODE[2]
0
Bit 1
R/W
MODE[1]
0
Bit 0
R/W
MODE[0]
0
This register configures operational modes of transmit links #3 to #31.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
MODE[2:0]:
The mode select bits (MODE[2:0]) configures the corresponding transmit link.
Table 28 details this procedure. When link 4m (0 m 7) is configured for
operation in 8.192 Mbps H-MVIP mode, links 4m+1, 4m+2 and 4m+3 are
driven with constant ones. However, links 4m+1, 4m+2 and 4m+3 must be
configured for 8.192 Mbps H-MVIP mode for correct operation of the
TCAS256. From a channel assignment point of view in the TCAS256
(Registers 0x400, 0x404), time-slots 0 through 31 of link 4m are mapped to
time-slots 0 through 31 of the H-MVIP link, time-slots 0 through 31 of link
4m+1 are mapped to time-slots 32 through 63 of the H-MVIP link, time-slots 0
through 31 of link 4m+2 are mapped to time-slots 64 through 95 of the H-
MVIP link and time-slots 0 through 31 of link 4m+3 are mapped to time-slots
96 through 127 of the H-MVIP link.