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RELEASED
DATA SHEET
PM7382 FREEDM-32P256
ISSUE 3
PMC-2010333
FRAME ENGINE AND DATA LINK MANAGER 32P256
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
151
CHAN[7:0]:
The indirect data bits (CHAN[7:0]) report the channel number read from the
RMAC256 internal memory after an indirect read operation has completed.
Channel number to be written to the RMAC256 internal memory in an indirect
write operation must be set up in this register before triggering the write.
CHAN[7:0] reflects the value written until the completion of a subsequent
indirect read operation.
PROV:
The indirect provision enable bit (PROV) reports the channel provision enable
flag read from the RMAC256 internal memory after an indirect read operation
has completed. The provision enable flag to be written to the RMAC256
internal memory, in an indirect write operation, must be set up in this register
before triggering the write. When PROV is set high, the channel indicated by
CHAN[7:0] is provisioned. When PROV is set low, the channel indicated by
CHAN[7:0] is unprovisioned temporarily. Any partially received packets are
flushed and the status in the RPDRR queue is marked unprovisioned. The
channel then returns to being provisioned and PROV will report a logic high
after the next indirect read operation. PROV reflects the value written until
the completion of a subsequent indirect read operation.
RWB:
The Read/Write Bar (RWB) bit selects between a provisioning/unprovisioning
operation (write) or a query operation (read). Writing a logic 0 to RWB
triggers the provisioning or unprovisioning of a channel as specified by
CHAN[7:0] and PROV. Writing a logic 1 to RWB triggers a query of the
channel specified by CHAN[7:0].
BUSY:
The indirect access status bit (BUSY) reports the progress of an indirect
access. BUSY is set high when this register is written to trigger an indirect
access, and will stay high until the access is complete. At which point, BUSY
will be set low. This register should be polled to determine when data from an
indirect read operation is available or to determine when a new indirect write
operation may commence.