![](http://datasheet.mmic.net.cn/330000/PM73487-PI_datasheet_16444394/PM73487-PI_211.png)
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATMTraffic Management Device
Released
Datasheet
199
After powerup or after a sustained software reset, the transmit and receive SDRAMs/SGRAMs
need to be initialized. The RX_DRAM_REGISTER runs in a burst-of-four mode, whereas the
TX_DRAM_REGISTER runs in a burst-of-eight mode, so the MODE register needs to be initial-
ized differently.
To initialize the SDRAM/SGRAM:
W-No op
W-Precharge both banks
W-Autorefresh
W-Autorefresh
W-Load
register
TX_DRAM_REGISTER)
Chip 0
00000000
h
93000000
h
A2000000
h
A2000000
h
Chip 1(SGRAM only)
00004000
h
93004000
h
h
A2004000
h
C2YY
(YY = 32
for
RX_DRAM_REGISTER,
33
for
C2320000
h
00000000
h
C2324000
h
00004000
h
W-No op
To write a location to the SDRAM/SGRAM (for example, location 0
h
in bank 0 with 55555555
h
):
W-Active bank 0
32000000
h
W-Write bank 0
26000000
h
32004000
h
26004000
h
To read the location of the SDRAM/SGRAM (for example, location 0
h
in bank 0):
W-Active bank 0
W-Read bank 0
R-
32000000
h
12000000
h
value of the DRAM location
32004000
h
12004000
h
To write a location to the SDRAM/SGRAM (for example, location 1234
h
in bank 1with
AAAAAAAA
h
):
W-Active bank 1
72120000
h
W-Write bank 1
6A340000
h
72124000
h
6A344000
h
9.5.1
RX_DRAM_REGISTER
Address: 2000000
h
(8000000
h
byte)
Type: Read/Write
Field (Bits)
Description
RX_DRAM_ACCESS_CODE
(31:28)
The access code to control the type of SDRAM/SGRAM cycle.
RX_DRAM_DATA
(27:26)
The data to be written to the DRAM. This 2-bit field is replicated 16 times and written
to the 32-bit wide SDRAM/SGRAM. Data of 00, 01, 10, and 11 correspond to DRAM
data 00000000
h
, 55555555
h
, AAAAAAAA
h
, and FFFFFFFF
h
. No other values of data
can be written to the SDRAM/SGRAM.
RX_DRAM_MI_SELECT
(25)
0
1
Normal operation.
Enables microprocessor access to the SDRAM/SGRAM.