![](http://datasheet.mmic.net.cn/330000/PM73487-PI_datasheet_16444394/PM73487-PI_189.png)
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATMTraffic Management Device
Released
Datasheet
177
9.2.3
Multicast Cell Instance Control Block (Internal Structure)
Base address: x
h
For input FIFOS (refer to
“AL_RAM_CONFIG” on page 105
):
If AL_RAM_CONFIG =
0
h
, the base address is 206000
h
(818000
h
byte).
If AL_RAM_CONFIG =
1
h
, the base address is 210000
h
(840000
h
byte).
If AL_RAM_CONFIG =
2
h
, the base address is 220000
h
(880000
h
byte).
If AL_RAM_CONFIG =
3
h
, the base address is 250000
h
(940000
h
byte).
For output FIFOS:
If AL_RAM_CONFIG =
0
h
, the base address is 208000
h
(820000
h
byte).
If AL_RAM_CONFIG =
1
h
, the base address is 214000
h
(850000
h
byte).
If AL_RAM_CONFIG =
2
h
, the base address is 214000
h
(850000
h
byte).
If AL_RAM_CONFIG =
3
h
, the base address is 258000
h
(960000
h
byte).
Index: 2
h
Entry number:
For input FIFOS (refer to
“AL_RAM_CONFIG” on page 105
):
If AL_RAM_CONFIG =
0
h
, the entry number is 512.
If AL_RAM_CONFIG =
1
h
, the entry number is 1K.
If AL_RAM_CONFIG =
2
h
, the entry number is 1K.
If AL_RAM_CONFIG =
3
h
, the entry number is 2K.
For output FIFOS:
If AL_RAM_CONFIG =
0
h
, the entry number is 32.
If AL_RAM_CONFIG =
1
h
, the entry number is 32.
If AL_RAM_CONFIG =
2
h
, the entry number is 32.
If AL_RAM_CONFIG =
3
h
, the entry number is 32.
Type: Read/Write
Byte
Offset
Long
Offset
Name
Read or
Write
Description
0
h
0
h
MC_HEADER_PTR
R/W (init only)
For the input FIFO, this is the OUTCHAN from the
cell. For the output FIFO, this is the pointer to the
entry in the MC header translation table for this entry.
4
h
1
h
MC_CELL_PTR
R/W (init only)
Pointer to the cell buffer containing the multicast cell
to be replicated.