![](http://datasheet.mmic.net.cn/330000/PM7347_datasheet_16444392/PM7347_121.png)
S/UNI-JET Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
121
Register 31EH: PMON FEBE/J2-EXZS Event Count LSB
Bit
Type
Function
Default
Bit 7
R
FEBE/J2-EXZS[7]
X
Bit 6
R
FEBE/J2-EXZS[6]
X
Bit 5
R
FEBE/J2-EXZS[5]
X
Bit 4
R
FEBE/J2-EXZS[4]
X
Bit 3
R
FEBE/J2-EXZS[3]
X
Bit 2
R
FEBE/J2-EXZS[2]
X
Bit 1
R
FEBE/J2-EXZS[1]
X
Bit 0
R
FEBE/J2-EXZS[0]
X
Register 31FH: PMON FEBE/J2-EXZS Event Count MSB
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
R
FEBE/J2-EXZS[13]
X
Bit 4
R
FEBE/J2-EXZS[12]
X
Bit 3
R
FEBE/J2-EXZS[11]
X
Bit 2
R
FEBE/J2-EXZS[10]
X
Bit 1
R
FEBE/J2-EXZS[9]
X
Bit 0
R
FEBE/J2-EXZS[8]
X
FEBE/J2-EXZS[13:0]
FEBE/J2-EXZS[13:0] represents the number of DS3 or E3 G.832 FEBEs that have been
detected since the last time the FEBE error counter was polled.
In J2 mode, FEBE/J2-EXZS[13:0] represents the number of Excessive Zeros (EXZS is a
string of eight or more consecutive zeros) that have occurred during the previous
accumulation interval.
The counter (and all other counters in the PMON) is polled by writing to any of the PMON
register addresses (314H to 31FH) or to the S/UNI-JET Identification, Master Reset, and
Global Monitor Update Register (006H). Such a write transfers the internally accumulated
count to the FEBE Event Count Registers and simultaneously resets the internal counter to
begin a new cycle of error accumulation. This transfer and reset is carried out in a manner
that coincident events are not lost. The transfer takes 255 RCLK cycles to complete in DS3
mode and three RCLK cycles to complete in E3 and J2 mode.