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參數(shù)資料
| 型號： | PLSI1032E-100LJ |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High-Density Programmable Logic |
| 中文描述： | EE PLD, 12.5 ns, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 212K |
| 代理商： | PLSI1032E-100LJ |
9
Specifications
ispLSI and pLSI 1032E
Internal Timing Parameters
1
t
ob
t
sl
1. Internal Timing Parameters are not tested and are for reference only.
Table 2-0037A/1032E
Outputs
UNITS
-100
MIN.
MIN.
MAX.
MAX.
DESCRIPTION
#
PARAM.
49 Output Buffer Delay
50 Output Buffer Delay, Slew Limited Adder
ns
ns
t
oen
t
odis
t
goe
51 I/O Cell OE to Output Enabled
52 I/O Cell OE to Output Disabled
53 Global OE
ns
ns
ns
t
gy0
t
gy1/2
t
gcp
t
ioy2/3
t
iocp
54 Clk Delay, Y0 to Global GLB Clk Line (Ref. clk)
ns
Global Reset
t
gr
Clocks
59 Global Reset to GLB and I/O Registers
ns
55 Clk Delay, Y1 or Y2 to Global GLB Clk Line
56 Clk Delay, Clock GLB to Global GLB Clk Line
57 Clk Delay, Y2 or Y3 to I/O Cell Global Clk Line
58 Clk Delay, Clk GLB to I/O Cell Global Clk Line
ns
ns
ns
ns
-125
–
–
–
–
–
1.5
1.5
0.8
0.0
0.8
–
2.0
10.0
5.1
5.1
3.9
1.5
4.3
1.5
1.8
0.0
1.8
–
–
–
–
–
1.4
1.4
0.8
0.0
0.8
–
1.3
9.9
4.3
4.3
2.7
1.4
2.8
1.4
1.8
0.0
1.8
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| PLSI1032E125LJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
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