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參數(shù)資料
| 型號(hào)： | PLSI1032E-100LJ |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High-Density Programmable Logic |
| 中文描述： | EE PLD, 12.5 ns, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大小： | 212K |
| 代理商： | PLSI1032E-100LJ |
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12
Specifications
ispLSI and pLSI 1032E
Maximum GRP Delay vs GLB Loads
GLB Load
3.0
5.0
1
8
16
32
G
4.0
4
2.0
6.0
GRP/GLB/1032E
ispLSI and pLSI 1032E-70
ispLSI and pLSI 1032E-90/100
ispLSI and pLSI 1032E-80
ispLSI and pLSI 1032E-125
1.0
Power Consumption
Figure 3. Typical Device Power Consumption vs fmax
Power consumption in the ispLSI and pLSI 1032E device
depends on two primary factors: the speed at which the
device is operating, and the number of product terms
used. Figure 3 shows the relationship between power
and operating speed.
0127/1032E
f
max (MHz)
Notes: Configuration of eight 16-bit counters
Typical current at 5V, 25
°
C
100
200
300
0
20
40
60
80
100
I
C
ispLSI and pLSI 1032E
250
150
350
125
150
I can be estimated for the ispLSI and pLSI 1032E using the following equation:
I (mA) = 15 + (# of PTs * 0.59) + (# of nets * Max freq * 0.0078)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The I estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of I is sensitive to operating
conditions and the program in the device, the actual I should be verified.
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| PLSI1032E125LJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
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| PLSI1032E80LJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
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