參數(shù)資料
型號(hào)： PIC18F87K90T-I/PT
廠商： Microchip Technology
文件頁(yè)數(shù)： 61/110頁(yè)
文件大?。?/td> 0K
描述： IC MCU 8BIT 128KB FLASH 80TQFP
標(biāo)準(zhǔn)包裝： 1,200
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 64MHz
連通性： I²C，LIN，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 69
程序存儲(chǔ)器容量： 128KB（64K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 24x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-TQFP
包裝： 帶卷 (TR)
2010 Microchip Technology Inc.
Preliminary
DS39964B-page 507
PIC18F47J53 FAMILY
ADDWF
ADD W to Indexed
(Indexed Literal Offset mode)
Syntax:
ADDWF
[k] {,d}
Operands:
0
k 95
d
[0,1]
Operation:
(W) + ((FSR2) + k)
dest
Status Affected:
N, OV, C, DC, Z
Encoding:
0010
01d0
kkkk
Description:
The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’ (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write to
destination
Example:
ADDWF
[OFST] ,0
Before Instruction
W
=
17h
OFST
=
2Ch
FSR2
=
0A00h
Contents
of 0A2Ch
=
20h
After Instruction
W
=
37h
Contents
of 0A2Ch
=
20h
BSF
Bit Set Indexed
(Indexed Literal Offset mode)
Syntax:
BSF [k], b
Operands:
0
f 95
0
b 7
Operation:
1 ((FSR2) + k)<b>
Status Affected:
None
Encoding:
1000
bbb0
kkkk
Description:
Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
BSF
[FLAG_OFST], 7
Before Instruction
FLAG_OFST
=
0Ah
FSR2
=
0A00h
Contents
of 0A0Ah
=
55h
After Instruction
Contents
of 0A0Ah
=
D5h
SETF
Set Indexed
(Indexed Literal Offset mode)
Syntax:
SETF [k]
Operands:
0
k 95
Operation:
FFh
((FSR2) + k)
Status Affected:
None
Encoding:
0110
1000
kkkk
Description:
The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write
register
Example:
SETF
[OFST]
Before Instruction
OFST
=
2Ch
FSR2
=
0A00h
Contents
of 0A2Ch
=
00h
After Instruction
Contents
of 0A2Ch
=
FFh
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