參數(shù)資料
型號： PIC18F87K90T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 29/110頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 128KB FLASH 80TQFP
標(biāo)準(zhǔn)包裝： 1,200
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 64MHz
連通性： I²C，LIN，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 69
程序存儲器容量： 128KB（64K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 24x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-TQFP
包裝： 帶卷 (TR)
PIC18F47J53 FAMILY
DS39964B-page 476
Preliminary
2010 Microchip Technology Inc.
COMF
Complement f
Syntax:
COMF
f {,d {,a}}
Operands:
0
f 255
d
[0,1]
a
[0,1]
Operation:
f
dest
Status Affected:
N, Z
Encoding:
0001
11da
ffff
Description:
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a(chǎn)’ is ‘0’, the Access Bank is selected.
If ‘a(chǎn)’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a(chǎn)’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
COMF
REG, 0, 0
Before Instruction
REG
=
13h
After Instruction
REG
=
13h
W=
ECh
CPFSEQ
Compare f with W, Skip if f = W
Syntax:
CPFSEQ
f {,a}
Operands:
0
f 255
a
[0,1]
Operation:
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
Status Affected:
None
Encoding:
0110
001a
ffff
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If ‘f’ = W, then the fetched instruction is
discarded and a NOP is executed
instead, making this a two-cycle
instruction.
If ‘a(chǎn)’ is ‘0’, the Access Bank is selected.
If ‘a(chǎn)’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a(chǎn)’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
CPFSEQ REG, 0
NEQUAL
:
EQUAL
:
Before Instruction
PC Address
=
HERE
W=
?
REG
=
?
After Instruction
If REG
=
W;
PC
=
Address (EQUAL)
If REG
W;
PC
=
Address (NEQUAL)
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