參數(shù)資料
型號： PIC18F87K90T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 106/110頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 128KB FLASH 80TQFP
標(biāo)準(zhǔn)包裝： 1,200
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 64MHz
連通性： I²C，LIN，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 69
程序存儲(chǔ)器容量： 128KB（64K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 24x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-TQFP
包裝： 帶卷 (TR)
PIC18F47J53 FAMILY
DS39964B-page 552
Preliminary
2010 Microchip Technology Inc.
TABLE 31-31: 10-BIT A/D CONVERSION REQUIREMENTS
TABLE 31-32: 12-BIT A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
130
TAD
A/D Clock Period
0.7
25.0(1)
sTOSC based, VREF 3.0V
131
TCNV
Conversion Time
(not including acquisition time)(2)
11
12
TAD
132
TACQ
Acquisition Time(3)
1.4
—
s-40C to +85C
135
TSWC
Switching Time from Convert
Sample
—
(Note 4)
137
TDIS
Discharge Time
0.2
—
s
Note 1:
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2:
ADRES registers may be read on the following TCY cycle.
3:
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the con-
version (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50W.
4:
On the following cycle of the device clock.
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
130
TAD
A/D Clock Period
0.8
12.5(1)
sTOSC based, VREF 3.0V
131
TCNV
Conversion Time
(not including acquisition time)(2)
13
14
TAD
132
TACQ
Acquisition Time(3)
1.4
—
s
135
TSWC
Switching Time from Convert
Sample
—
(Note 4)
137
TDIS
Discharge Time
0.2
—
s
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50
.
4: On the following cycle of the device clock.
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