PIC18F2423/2523/4423/4523
DS39755B-page 46
Preliminary
2007 Microchip Technology Inc.
FIGURE 4-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
DD
, V
DD
RISE < T
PWRT
)
FIGURE 4-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR RISES BEFORE T
OST
COMPLETES)
FIGURE 4-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR RISES AFTER T
OST
COMPLETES)
T
PWRT
T
OST
V
DD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
OSC1
T
PWRT
T
OST
V
DD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
OSC1
V
DD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
T
PWRT
T
OST
OSC1