參數(shù)資料
型號: PIC18F44J50-I/ML
廠商: Microchip Technology
文件頁數(shù): 15/32頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 16K 2V 44-QFN
產(chǎn)品培訓(xùn)模塊: XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 45
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2.15 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VQFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 656 (CN2011-ZH PDF)
配用: AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
PIC18F2XJXX/4XJXX FAMILY
DS39687E-page 22
2009 Microchip Technology Inc.
DSWTPS<3:0>
CONFIG3L
Deep Sleep Watchdog Timer Postscale Select bits
The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms.
1111 = 1:2,147,483,648 (25.7 days)
1110 = 1:536,870,912 (6.4 days)
1101 = 1:134,217,728 (38.5 hours)
1100 = 1:33,554,432 (9.6 hours)
1011 = 1:8,388,608 (2.4 hours)
1010 = 1:2,097,152 (36 minutes)
1001 = 1:524,288 (9 minutes)
1000 = 1:131,072 (135 seconds)
0111 = 1:32,768 (34 seconds)
0110 = 1:8,192 (8.5 seconds)
0101 = 1:2,048 (2.1 seconds)
0100 = 1:512 (528 ms)
0011 = 1:128 (132 ms)
0010 = 1:32 (33 ms)
0001 = 1:8 (8.3 ms)
0000 = 1:2 (2.1 ms)
DSWDTEN
CONFIG3L
Deep Sleep Watchdog Timer Enable bit
1 = DSWDT enabled
0 = DSWDT disabled
DSBOREN
CONFIG3L
Deep Sleep BOR Enable bit
1 = BOR enabled in Deep Sleep
0 = BOR disabled in Deep Sleep (does not affect operation in non Deep Sleep modes)
RTCOSC
CONFIG3L
RTCC Reference Clock Select bit
1 = RTCC uses T1OSC/T1CKI as reference clock
0 = RTCC uses INTRC as reference clock
DSWDTOSC
CONFIG3L
DSWDT Reference Clock Select bit
1 = DSWDT uses INTRC as reference clock
0 = DSWDT uses T1OSC/T1CKI as reference clock
MSSPMSK(1,2)
CONFIG3H
MSSP 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode enable
0 = 5-Bit Address Masking mode enable
IOL1WAY
CONFIG3H
IOLOCK Bit One-Way Set Enable bit
1 = The IOLOCK bit (PPSCON<0>) can be set once, provided the unlock sequence has
been completed. Once set, the Peripheral Pin Select registers cannot be written to a
second time.
0 = The IOLOCK bit (PPSCON<0>) can be set and cleared as needed, provided the
unlock sequence has been completed
WPCFG(4)
CONFIG4L
Write/Erase Protect Configuration Words Page bit (valid when WPDIS = 0)
1 = Configuration Words page is not erase/write-protected unless WPEND and
WPFP<5:0> settings include the Configuration Words page
0 = Configuration Words page is erase/write-protected, regardless of WPEND and
WPFP<5:0> settings
WPEND
CONFIG4L
Write/Erase Protect Region Select bit (valid when WPDIS = 0)
1 = Flash pages, WPFP<5:0> to Configuration Words page, are write/erase-protected
0 = Flash pages, 0 to WPFP<5:0> are write/erase-protected
TABLE 5-5:
PIC18F46J11 AND PIC18F46J50 FAMILY DEVICES: BIT DESCRIPTIONS (CONTINUED)
Bit Name
Configuration
Words
Description
Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.
2: The Configuration bits are reset to ‘1’ only on VDD Reset; it is reloaded with the programmed value at any device Reset.
3: These bits are not implemented in PIC18F46J11 family devices.
4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code
protection, perform an ICSP Bulk Erase operation.
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