參數(shù)資料
型號: PIC18F44J50-I/ML
廠商: Microchip Technology
文件頁數(shù): 11/32頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 16K 2V 44-QFN
產(chǎn)品培訓模塊: XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標準包裝: 45
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設備: 欠壓檢測/復位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2.15 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 13x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VQFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 656 (CN2011-ZH PDF)
配用: AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
2009 Microchip Technology Inc.
DS39687E-page 19
PIC18F2XJXX/4XJXX FAMILY
TABLE 5-3:
PIC18F45J10 FAMILY DEVICES: BIT DESCRIPTIONS
Bit Name
Configuration
Words
Description
DEBUG
CONFIG1L
Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general
purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to in-circuit debug
XINST
CONFIG1L
Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled
(Legacy mode)
STVREN
CONFIG1L
Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow enabled
0 = Reset on stack overflow/underflow disabled
WDTEN
CONFIG1L
Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
CP0
CONFIG1H
Code Protection bit
1 = Program memory is not code-protected
0 = Program memory is code-protected
IESO
CONFIG2L
Internal/External Oscillator Switchover bit
1 = Oscillator Switchover mode enabled
0 = Oscillator Switchover mode disabled
FCMEN
CONFIG2L
Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor enabled
0 = Fail-Safe Clock Monitor disabled
FOSC2
CONFIG2L
Default Oscillator Select bit
1 = Clock designated by FOSC<1:0> is enabled as system clock when
OSCCON<1:0> = 00
0 = INTRC is enabled as system clock when OSCCON<1:0> = 00
FOSC<1:0>
CONFIG2L
Primary Oscillator Select bits
11 = EC oscillator, PLL enabled and under software control, CLKO function on OSC2
10 = EC oscillator, CLKO function on OSC2
01 = HS oscillator, PLL enabled and under software control
00 = HS oscillator
WDTPS<3:0>
CONFIG2H
Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
CCP2MX
CONFIG3H
CCP2 MUX bit
1 = CCP2 is multiplexed with RC1
0 = CCP2 is multiplexed with RB3
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